Abstract
Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.
Highlights
Nowadays, ̄eld-programmable gate array (FPGA) is widely used in variouselds, such as rapid prototyping,[1,2] fast audio/video processing,[3,4,5,6] etc
Several researches on arithmetic circuit using the SD number representation on FPGA19–26 are reported
We propose a new SD carry-free addition algorithm and show that its implementation on FPGA is smaller than the conventional SD adder
Summary
Nowadays, ̄eld-programmable gate array (FPGA) is widely used in variouselds, such as rapid prototyping,[1,2] fast audio/video processing,[3,4,5,6] etc. There are several addition algorithms without long carry chain[7,8,9,10,11,12] based on such property. These algorithms perform addition in constant time, even when the lengths of the operands are long. We propose a new SD carry-free addition algorithm and show that its implementation on FPGA is smaller than the conventional SD adder. This paper is organized as follows: Section 2 presents the SD number system and its representation as well as an addition algorithm.
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