Signed-digit Number System Research Articles

Algorithms for optoelectronic implementation of modified signed-digit division, square-root, logarithmic, and exponential functions

Algorithms for computing complex elementary functions based on the modified signed-digit (MSD) number system representations are proposed. An arithmetic unit that performs parallel one-step addition (subtraction), multiplication, and division is proposed to achieve the computation of complex functions such as the square-root, logarithm, exponential, and other related operations. An optoelectronic correlator-based architecture is suggested for implementing the proposed MSD algorithms to compute the above-mentioned elementary functions. We utilized the symbolic substitution technique to reduce the number of computation rules involved.

Trinary signed-digit arithmetic using an efficient encoding scheme

The trinary signed-digit (TSD) number system is of interest for ultrafast optoelectronic computing systems since it permits parallel carry-free addition and borrow-free subtraction of two arbitrary length numbers in constant time. In this paper, a simple coding scheme is proposed to encode the decimal number directly into the TSD form. The coding scheme enables one to perform parallel one-step TSD arithmetic operation. The proposed coding scheme uses only a 5-combination coding table instead of the 625-combination table reported recently for recoded TSD arithmetic technique.

Modified signed-digit trinary addition using synthetic wavelet filter

The modified signed-digit (MSD) number system has been a topic of interest as it allows for parallel carry-free addition of two numbers for digital optical computing. In this paper, harmonic wavelet joint transform (HWJT)-based correlation technique is introduced for optical implementation of MSD trinary adder implementation. The realization of the carry-propagation-free addition of MSD trinary numerals is demonstrated using synthetic HWJT correlator model. It is also shown that the proposed synthetic wavelet filter-based correlator shows high performance in logic processing. Simulation results are presented to validate the performance of the proposed technique.

Parallel computation of complex elementary functions using quaternary signed-digit arithmetic

A variety of algorithms for computing complex elementary functions based on the quaternary signed-digit (QSD) number system are proposed. An arithmetic unit that performs parallel one-step addition (subtraction), multiplication, and division is proposed to perform the computations of elementary functions such as square root, logarithmic, exponential, and other related functions. An optoelectronic-correlator-based architecture is suggested for implementing the proposed QSD elementary function algorithms. We used the symbolic substitution technique to reduce the number of the computation rules involved.

Parallel optoelectronic trinary signed-digit division

The trinary signed-digit (TSD) number system has been found to be very useful for parallel addition and subtraction of any arbitrary length operands in constant time. Using the TSD addition and multiplication modules as the basic building blocks, we develop an efficient algorithm for performing parallel TSD division in constant time. The proposed division technique uses one TSD subtraction and two TSD multiplication steps. An optoelectronic correlator based architecture is suggested for implementation of the proposed TSD division algorithm, which fully exploits the parallelism and high processing speed of optics. An efficient spatial encoding scheme is used to ensure better utilization of space bandwidth product of the spatial light modulators used in the optoelectronic implementation.

Multiple-input neuron MOS operational amplifier for voltage-mode multivalued full adders

A CMOS operational amplifier employing the multiple-input-terminal transistor called neuron MOSFET (or /spl nu/MOS) as pair transistors has been developed. The circuit can perform a variety of analog voltage summation/subtraction operations in a very simple circuitry. The self-offset-cancellation capability has been implemented by a clocked /spl nu/MOS technique. As a result, high-accuracy voltage-mode signed-digit computation has become possible. The /spl nu/MOS operational amplifier has been applied to build a carry-propagation-free multivalued full adder circuit based on the radix-4 seven-valued signed-digit number system. The circuit operation has been verified by test circuits fabricated by Tohoku University standard double-polysilicon CMOS process with a 3 /spl mu/m rule.

Optical modified signed‐digit addition module based on Boolean polarization‐encoded logic algebra

The modified signed-digit (MSD) number system satisfies the requirements of totally parallel addition using identical units and enables the addition of any two numbers in three sucessive steps. We show a simple and compact design of the parallel optical addition module based on MSD number representation using Boolean polarization-encoded logic algebra (BPLA). The four transforms of MSD addition are ex- pressed mathematically and the realization of the transform module us- ing liquid crystal devices (LCDs) are also given. © 1996 Society of Photo- Optical Instrumentation Engineers.

Canonical quaternary signed-digit arithmetic using optoelectronics symbolic substitution

A higher radix based signed-digit number system, such as the quaternary signed-digit (QSD) number system, allows higher information storage density, less complexity, fewer system components, and fewer cascaded gates and operations. An optoelectronics symbolic substitution scheme to handle the parallel quaternary signed-digit (QSD) arithmetic operations is proposed. A conversion algorithm is employed on the QSD numbers to simplify the addition process and reduce the number of the optical symbolic substitution rules. The optical addition operation of two QSD numbers is performed in one-step. An efficient shared content-addressable memory (SCAM)-based optical implementation of the QSD addition/subtraction operations employs a fixed number of minterms for any operand length. The canonical QSD number addition/subtraction scheme requires a significantly reduced number of minterms when compared with a similar previously reported technique.

High-radix signed-digit arithmetic using symbolic substitution computations

High-radix number representations such as the quaternary signed-digit (QSD) number system allow higher information storage density, less complexity, fewer system components, and fewer cascaded gates and operations. Arithmetic operations on the quaternary signed-digit are carried out using the powerful symbolic substitution scheme. A single-step or two-step conversion algorithm is employed on the QSD numbers to simplify the higher-order QSD addition process and reduce the number of the optical symbolic substitution rules. The optical addition operation of two QSD numbers is performed in one step. An efficient content-addressable memory (CAM) optical implementation of the QSD addition/subtraction operations is proposed. The QSD number addition/subtraction operations require a significantly reduced number of minterms (symbolic substitution rules) when compared to a similar previously reported technique.

Self-timed divider using the redundant signed digit number system

A divider structure that combines a novel self-limed ring structure and a carry-propagation-free division algorithm is proposed. The self-timed ring structure enables the divider to compute at a speed comparable to that of previously designed dividers but with less silicon area. By exploiting the carry-propagation-free division algorithm, even better performance can be achieved. A 54-bit divider employing the proposed structure and a non-overlapped scheme has been implemented in 1-2μm CMOS technology, obtaining a speed of 193 ns per worst-case division on 4-3 mm 2 of silicon area.

Symbolic substitution by means of one-of-many coding

Symbolic substitution (SS) for digital optical computing initially used intensity coding with one pixel representing one bit. This required recognition of both the dark and the bright pixels in a pattern for complete recognition. To avoid this double recognition, dual-rail coding was introduced, where it is sufficient to recognize either the dark or the bright pixels alone for complete recognition. Subsequently, the modified signed-digit number system was proposed to fully exploit the parallelism of SS for arithmetic operations. This introduces a third symbol - 1 , and with dual-rail coding, this again necessitates recognition of both dark and bright pixels. We argue the usefulness of triple-rail coding to avoid this double recognition. We show that the nature of this one-of-three coding enables simplified recognition of a set of patterns. We present a new implementation of SS based on this coding. We also show that this one-of-many coding can be extended to high-radix arithmetic with equal efficiency. We present an evaluation scheme based on the number of optical hardware elements required by each implementation and use it to compare the different implementations of SS.

Modified signed-digit arithmetic based on redundant bit representation

Fully parallel modified signed-digit arithmetic operations are realized based on redundant bit representation of the digits proposed. A new truth-table minimizing technique is presented based on redundant-bitrepresentation coding. It is shown that only 34 minterms are enough for implementing one-step modified signed-digit addition and subtraction with this new representation. Two optical implementation schemes, correlation and matrix multiplication, are described. Experimental demonstrations of the correlation architecture are presented. Both architectures use fixed minterm masks for arbitrary-length operands, taking full advantage of the parallelism of the modified signed-digit number system and optics.

Efficient trinary signed-digit symbolic arithmetic

A new technique for high-speed trinary signed-digit (TSD) arithmetic that uses optical symbolic substitution is presented. This technique performs multibit carry-free addition and borrow-free subtraction in constant time. The proposed TSD scheme utilizes the minimum number of minterms compared with the previously reported modified signed-digit and TSD number systems.

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

A novel hybrid number representation is proposed. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New redundant representations of complex numbers and vectors

The authors present a redundant representation for complex numbers called polygonal representation. This representation enables fast carry-free addition, in a way quite similar to the carry-free addition in signed-digit number systems and is convenient for multiplication. The technique is generalized in order to handle n-dimensional vectors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hybrid signed digit logarithmic number system processor

A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. The hybrid SD/LNS processor exploits the parallelism that is offered by the SD number system to boost the performance of the fast LNS processors, and compares favourably to conventional LNS processor designs.

On the implementation of arithmetic support functions for generalized signed-digit number systems

Ordinary signed-digit (OSD) number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha . . .,-1,0,1. . ., alpha ), where alpha is an arbitrary integer in the range r/2 0 and beta >0) explicitly. Zero detection, sign detection, and overflow handling are also treated in depth. >

Very-high-speed VLSI 2s-complement multiplier using signed binary digits

A high-speed 8*8-bit multiplier design for 2s-complement binary numbers is presented. The multiplier uses the binary signed-digit number system to achieve both high speed and layout simplicity, and is implemented in double layer metal 2 mu m CMOS technology. The multiplication time for the array was found by simulation to be 18 ns at 25 degrees C and its size was measured as 1.7 mm*2.3 mm (excluding pads). Power dissipation was calculated as just less than 40 mW at 55 MHz, and the transistor count is 3754 transistors.

High-speed multiplier for digital signal processing

A high-speed optical system capable of performing <i>n</i>-bit multiplication in a time proportional to log₂<i>n</i> is presented. The simultaneous generation and the optical regrouping of all the partial products and the pairwise addition of the partial products by means of a binary tree of adders capable of adding any two numbers in a single stage (by completely eliminating the carry propagation chain) are unique features of this multiplier. The input data to the multiplier can be in either a binary or a modified signed digit number system. The simultaneous generation and the pairwise addition of the partial products are accomplished by means of the principle of symbolic substitution logic that was originally proposed by Brenner.

Radix-2 SRT division algorithm with simple quotient digit selection

A new and fast algorithm for SRT division that combines a modified version of the Svoboda algorithm with the radix-2 signed-digit number system is presented. The quotient bit selection is a simple function of the two most significant digits of the current partial remainder, and the two operands are each prescaled by a single subtraction.