Abstract
This work looks at optimizing finite impulse response (FIR) filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-and-routed. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization
Highlights
Digital signal processing (DSP) systems employ computer systems to digitally process input signals
As all the computing platforms that are used today for digital signal processing are based on digital electronics, the arithmetic operations they perform should be handled in a way that is suitable to the nature of the electronics that build these platforms
In the applications that involve multiple constant multiplications (MCM) as in the finite impulse response (FIR) filters, using canonic signed-digit (CSD) guarantees the minimal number of adders
Summary
Digital signal processing (DSP) systems employ computer systems to digitally process input signals. The hardware complexity and processing delay of these digital filters are proportional to a parameter called the filter order, which is highly desired to be large [1]. These filters have been built using FPGA’s [2] [3] [4]. Computers use radix-2, there have been few number systems discussed in the computer arithmetic literature that are unconventional in terms of representation and operations. Such number systems are used in computers for some special applications
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