Signal-to-noise-and-distortion Research Articles

A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis

This study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18[Formula: see text][Formula: see text]m CMOS process. For a 51.514[Formula: see text]kHz sinusoidal 1[Formula: see text]V peak-to-peak differential input signal with a 1[Formula: see text]MSPs clock speed, the proposed circuit achieves 2.0141[Formula: see text]mV maximum sampling window error, 0.131[Formula: see text][Formula: see text]W power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

This paper proposes a VCO-based ADC with first-order noise shaping for EEG signal recording front ends. Addressing the challenge of applying analog integrators in advanced processes due to low voltage issues, a multi-phase quantizer structure is introduced based on V-F conversion within the VCO structure, resulting in lower analog power consumption at the same output bit-width. By introducing a form of Gray code encoding, errors caused by circuit metastability are limited to within 1 bit. Considering the effects of motion artifacts and the electrode DC offset, the circuit achieves a wide input range of 500 mVpp by adjusting the feedback coefficients. A prototype ADC is fabricated using 180 nm CMOS technology, operating at a 1.8 V/1 V power supply voltage, with power consumption of 17.1 μW, while achieving a 62.1 dB signal-to-noise and distortion ratio (SNDR) and 55.2 dB dynamic range (DR). The proposed ADC exhibits input noise of 8.64 μVrms within a bandwidth of 0.5 Hz–5 kHz.

A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications.

A second-order voltage-controlled oscillator (VCO)-based continuous-time sigma-delta modulator (CTSDM) for current-sensing readout applications is proposed. Current signals from the sensor can directly be quantized by the proposed VCO-based CTSDM, which does not require any extra trans-impedance amplifiers. With the proportional-integral (PI) structure and a VCO phase integrator, the capability of second-order noise shaping is available to reduce the in-band quantization noise. The PI structure can be simply realized by a resistor in series with the integrating capacitor, which can reduce the architecture complexity and maintain the stability of the system. The current-steering digital-to-analog converter with tail and sink current sources is used on the feedback path for the subtraction of the current-type input signal. All the components of the circuit are scaling friendly and applicable to current-sensing readout applications in the Internet of Things (IoT). The proposed VCO-based CTSDM implemented in a 0.18-μm standard CMOS process has a measured signal-to-noise and distortion ratio (SNDR) of 74.6 dB at 10 kHz bandwidth and consumes 44.8 μw only under a supply voltage of 1.2 V, which can achieve a Figure-of-Merit (FoM) of 160.76 dB.

Baseline Calibration Scheme Embedded in Single-Slope ADC for Gas Sensor Applications

This paper introduces a single-slope analog-to-digital converter (SS ADC) with an embedded digital baseline calibration scheme designed to improve the accuracy and reliability of gas sensor measurements. The proposed SS ADC effectively leverages an up/down counter mechanism to ensure stable signal extraction from gas sensors, despite variations in the baseline distribution. The proposed SS ADC initiates with a down counting operation to capture the initial output value of the gas sensor, which, after A/D conversion, is stored as a reference point for future readings. Subsequent gas sensor output values are derived by performing an up counting operation from this baseline reference. This approach allows for real-time correction of the baseline during the SS A/D conversion process, obviating the need for complex post-processing and baseline correction algorithms. The proposed SS ADC with the baseline calibration scheme was designed using a 0.18 μm standard CMOS process to confirm its feasibility. It demonstrated a signal-to-noise and distortion ratio (SNDR) of 57.56 dB and a spurious-free dynamic range (SFDR) of 59.02 dB, resulting in an effective number of bits (ENOB) of 9.27 bits in the post-simulation level. The proposed SS ADC has a total power consumption of 1.649 mW. This work offers an efficient solution to the baseline distribution problem in gas sensors, facilitating more reliable and accurate gas detection systems.

A 12 μW 10 kHz BW 58.9 dB SNDR AC-Coupled Incremental ADC for Neural Recording

This paper presents an AC-coupled, incremental analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural recording. It achieves a rail-to-rail electrode DC offset (EDO) rejection, low noise, a small area, and low power consumption. Fabricated in a 180 nm CMOS process, the prototype ADC achieves a high input impedance, 24 mVpp linear input range, and 58.9 dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 12 μW and an area of 0.0192 mm2. The referred-to-input (RTI) noise is 6.9 μVrms within the bandwidth of 1 Hz–10 kHz.

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD).

Improved PGC demodulation algorithm for fiber optic interferometric sensors.

An improved phase generated carrier arctangent demodulation algorithm based on harmonic mixing and phase quadrature technology (PGC-Arctan-HP) is proposed in this paper, which can eliminate the effects of modulation depth shift, carrier phase delay, and light intensity disturbance (LID) on the demodulation results. The simulation results are consistent with theoretical analysis, and indicate that the PGC-Arctan-HP algorithm can achieve optimal demodulation compared with other demodulation algorithms. The results of interferometric experiments show that the demodulated waveforms of the improved algorithm are relatively stable with an amplitude error of 0.0294%. The total-harmonic-distortion (THD) and the signal-to-noise-and-distortion (SINAD) can reach -60.0286 dB and 59.5388 dB.

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power consumption. The buffer and the ADC are fabricated in a 0.18-μm CMOS process with an active area of 2.41 mm2, with 3∼5V supply voltage for the input buffer and 1.8-V power supply for the ADC, the overall ADC chip achieves a signal-to-noise-and-distortion ratio (SNDR) of 103.3 dB, a spurious-free dynamic range (SFDR) of 113.2 dB and an integral nonlinearity (INL) of ±2.5 ppm/full-scale range (FSR). The overall power consumption is 14.88 mW.

A Wirelessly Powered Scattered Neural Recording Wearable System.

This paper introduces a wirelessly powered scattered neural recording wearable system that can facilitate continuous, untethered, and long-term electroencephalogram (EEG) recording. The proposed system, including 32 standalone EEG recording devices and a central controller, is incorporated in a wearable form factor. The standalone devices are sparsely distributed on the scalp, allowing for flexible placement and varying quantities to provide extensive spatial coverage and scalability. Each standalone device featuring a low-power EEG recording application-specific integrated circuit (ASIC) wirelessly receives power through a 60 MHz inductive link. The low-power ASIC design (84.6 μW) ensures sufficient wireless power reception through a small receiver (Rx) coil. The 60 MHz inductive link also serves as the data carrier for wireless communication between standalone devices and the central controller, eliminating the need for additional data antennas. All these efforts contribute to the miniaturization of standalone devices with dimensions of 12×12×5 mm3, enhancing device wearability. The central controller applies the pulse width modulation (PWM) scheme on the 60 MHz carrier, transmitting user commands at 4 Mbps to EEG recording ASICs. The ASIC employs a novel synchronized PWM demodulator to extract user commands, operating signal digitization and data transmission. The analog frontend (AFE) amplifies the EEG signal with a gain of 45 dB and applies band-pass filtering from 0.03 Hz to 400 Hz, with an input-referred noise (IRN) of 3.62 μVRMS. The amplified EEG signal is then digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a peak signal-to-noise and distortion ratio (SNDR) of 55.4 dB. The resulting EEG data is transmitted to an external software-defined radio (SDR) Rx through load-shift-keying (LSK) backscatter at 3.75 Mbps. The system's functionality is fully evaluated in human experiments.

A Wireless Multimodal Physiological Monitoring ASIC for Animal Health Monitoring Injectable Devices.

Utilizing injectable devices for monitoring animal health offers several advantages over traditional wearable devices, including improved signal-to-noise ratio (SNR) and enhanced immunity to motion artifacts. We present a wireless application-specific integrated circuit (ASIC) for injectable devices. The ASIC has multiple physiological sensing modalities including body temperature monitoring, electrocardiography (ECG), and photoplethysmography (PPG). The ASIC fabricated using the CMOS 180 nm process is sized to fit into an injectable microchip implant. The ASIC features a low-power design, drawing an average DC power of 155.3 μW, enabling the ASIC to be wirelessly powered through an inductive link. To capture the ECG signal, we designed the ECG analog frontend (AFE) with 0.3 Hz low cut-off frequency and 45-79 dB adjustable midband gain. To measure PPG, we employ an energy-efficient and safe switched-capacitor-based (SC) light emitting diode (LED) driver to illuminate an LED with milliampere-level current pulses. A SC integrator-based AFE converts the current of photodiode with a programmable transimpedance gain. A resistor-based Wheatstone Bridge (WhB) temperature sensor followed by an instrumentation amplifier (IA) provides 27-47 °C sensing range with 0.02 °C inaccuracy. Recorded physiological signals are sequentially sampled and quantized by a 10-bit analog-to-digital converter (ADC) with the successive approximation register (SAR) architecture. The SAR ADC features an energy-efficient switching scheme and achieves a 57.5 dB signal-to-noise-and-distortion ratio (SNDR) within 1 kHz bandwidth. Then, a back data telemetry transmits the baseband data via a backscatter scheme with intermediate-frequency assistance. The ASIC's overall functionality and performance has been evaluated through an in vivo experiment.

A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique

This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based ΔΣ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW.

A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS

In this paper, we propose a merge-mismatch-error-shaping (M-MES) noise shaping SAR ADC as a solution to address the limitation of SNDR caused by the non-linearity resulting from DAC mismatch. The proposed M-MES technique is based on MES with the introduction of capacitive merging to mitigate the degradation of dynamic range (DR) in ADCs. In addition, to meet the high signal-to-noise ratio (SNR) and low power requirements of the ADC, cascaded integrator feed-forward (CIFF) noise shaping ADC in this paper is a first-order filter based on a closed-loop amplifier. The proposed ADC was simulated and designed in a 180-nm CMOS process, which consumes 449 μW of power when operating at 1 MS/s sampling frequency. According to the post-simulation results, under a 3.3-V supply and at an oversampling ratio (OSR) of 500, the proposed ADC achieves Schreier FoMS of 168.5 dB with 102.1 dB signal to noise and distortion ratio (SNDR) and 102.2 dB spurious free dynamic range (SFDR).

A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT

This paper presents a 12-bit 1.6 GS/s pipelined analog-to-digital converter (ADC) in a 40-nm CMOS process. A novel dual-capacitor dither injection technique was proposed, based on a randomize multi-level uniform logic, aimed at leveraging multi-level signal jitter to disperse higher-order harmonics and spurious signals within the spectrum. The technique proves highly effective in preserving the linearity of high-speed pipeline ADCs under Process, Voltage, and Temperature (PVT) variations. Additionally, a high-speed amplifier with SC net was designed, and its matching bias circuit design can achieve configurable performance adjustment according to circumstances. Measurement results show that the ADC attains an impressive Signal-to-Noise and Distortion Ratio (SNDR) of 55.9 dB and Spurious-Free Dynamic Range (SFDR) of 71.7 dB at the Nyquist frequency. Furthermore, the SFDR variation remains below 4.2 dB over the temperature range of −40 °C–85 °C.

A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit

In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices, a bridged-switch energy-efficient switching scheme for successive approximation register (SAR) ADCs with a low-complexity capacitor drive circuit is proposed. The technique of top-plate sampling and closed-loop charge recycling is used in the proposed switching scheme so that neither the first nor the second comparison consumes switching energy. The third comparison uses bridge switches to connect the subarray to the main array, effectively reducing switching’s energy consumption. Only the least significant bit (LSB) is dependent on the accuracy of Vcm; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV2ref, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

A Low-Distortion Low-Power MASH Architecture ΣΔ Modulator with Double-Sampling

This paper presents a low-distortion and low-power multi-stage noise-shaping (MASH) architecture Sigma-Delta ([Formula: see text] modulator with double-sampling. The modulator uses a cascade of integrator feed-forward (CIFF) structure as a cascaded modulator in a MASH architecture. Since the CIFF structure provides a feedforward path from the input signal to the quantizer, the input signal is directly transmitted to the output without loop processing, relaxing the linearity requirement of the modulator, reducing performance requirements for the OTA and harmonic distortion. Double-sampling technique is adopted in the first integrator to double the sampling rate, improving the accuracy of the modulator without the increase of power consumption. In order to eliminate the influence of capacitor mismatch in the sampling network, a fully floating differential switched capacitor (SC) feedback digital-to-analog (DAC) is used in the integrator. The simulation results show that the [Formula: see text] modulator achieves 113[Formula: see text]dB signal-to-noise and distortion ratio (SNDR) and the power consumption is 3.15[Formula: see text]mW from a 5[Formula: see text]V power supply.

An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications

This article presents an innovative architecture and design of an 8-bits Effective-Number-of-Bits (ENOB) Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC), aiming at activity-driven multi-channel Complementary-Metal-Oxide-Semiconductor (CMOS) readout Application-Specific-Integrated-Circuits (ASICs) for imaging and spectroscopic applications in space field. The proposed ADC needs only a single low duty-cycle clock signal ‘CLKSampling’ to initiate the conversion process and generates all other required clock signals internally. Unlike conventional ASAR ADCs, this ADC makes use of a unique rising edge only variable delay-cell to introduce desired delay values to the internally generated clock signal. In addition, the ADC features sampling-rate (fs)-reconfigurability, from typical 40 kHz to 167 kHz, with a proportional power consumption. Also, the proposed architecture is flexible with respect to the time-period and duty-cycle of the ‘CLKSampling’ signal, that can be tailored keeping in view the primary requirements of the desired applications. Moreover, the proposed design is equipped with a simple metastability watchdog circuitry. Fabricated in a 0.35 µm CMOS process at 3.3 V supply, the ADC secures a measured ENOB, and Signal-to-Noise-and-Distortion-Ratio (SNDR) of 7.76-bits, and 48.47 dB, respectively at the typical fs of 40 kHz. Measured Integral-Non-Linearity (INL), and Differential-Non-Linearity (DNL) are within one LSB. The ADC normalized figure-of-merit (FoMWN) - proposed to fairly compare high voltage-based ADCs with low voltage-based ADCs - is 476 fJ/C-step at its maximum fs with all the sections of the ADC operating at 3.3 V. The FoMWN improves to 261.7 fJ/c-step and 243 fJ/c-step with the digital section and delay-cell operated at 1.2 V with and without level-shifters power contribution, respectively without any performance deterioration.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.