Signal Integrity Issues Research Articles

Detection of Signal Integrity Issues in Vibration Monitoring Using One-Class Support Vector Machine

AbstractThis paper presents an analysis of the common signal integrity issues in vibration monitoring caused by sensor saturation and signal distortion, or sensor loosening and detachment, and the development of a method of detecting the occurrence of vibration signal integrity issues using a one-class support vector machine. For this, vibration signals with distortions due to sensor saturation and/or sensor detachment are analysed to determine parameters sensitive to common integrity issues. These features are then extracted from training data of good quality vibration signals. Principal Component Analysis is used to dimensionally reduce the parameters which are then used in the training of the one-class support vector machine. The proposed method was validated on trained and untrained health conditions. Additionally, model sensitivity was also tested on trained health conditions with varying defect sizes. The method successfully detected all signal integrity issues tested proving to be an effective pre-processing step in condition monitoring systems for increased reliability and accuracy.

Analyzing the impact of parasitics on a CMOS-Memristive crossbar neural network based on winner-take-all and Hebbian rule

For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 nJ energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.

A Low-power DRAM Controller ASIC with a 36% Reduction in Average Active Power by Increasing On-die Termination Resistance

A low-power DRAM controller ASIC is proposed for point-to-point interconnects such as deep learning applications. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power consumption with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid signal integrity issues. The proposed DRAM controller is implemented in a 65 nm process with an active area of 1.64 mm², 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed controller and a commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the TX current of a clock signal is minimized when the time of flight of the PCB channel is integer multiples of the half period of the clock signal with large TX and RX terminations.

Signal Integrity Analysis of Neuronal Spike Signal in 3-D Packaging

Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural network (ANN), SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity problems in 3-D packaging. In this paper, the RLGC equivalent circuit of through-silicon vias (TSV) and redistribution layers (RDL) structure were modeled in 3-D packaging. Furthermore, the spike signal integrity (SI) issues, such as reflection, delay and loss of spike signal, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself but not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This paper presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.

Modeling and Signal Integrity Analysis of RRAM-Based Neuromorphic Chip Crossbar Array Using Partial Equivalent Element Circuit (PEEC) Method

This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50\times 50$ </tex-math></inline-formula> array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy.

An Innovative Architecture of Full-Digital Microphone Arrays Over A²B Network for Consumer Electronics

Microphone arrays of various sizes and shapes are currently employed in consumer electronics devices such as speakerphones, smart TVs, smartphones, and headphones. In this paper, a full-digital, planar microphone array is presented. It makes use of digital Micro Electro-Mechanical Systems (MEMS) microphones, connected through the Automotive Audio Bus (A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> B). A clock propagation model for A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> B networks, developed in a previous work, was employed to estimate the effects of jitter and delay on microphone arrays. It will be shown that A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> B allows for a robust data transmission, while ensuring deterministic latency and channels synchronization, thus overcoming the signal integrity issues which usually affect MEMS capsules. The microphone positioning is also discussed since it greatly affects the spatial accuracy of beamforming. Numerical simulations were performed on four regular geometries to identify the optimal layout in terms of number of capsules and beamforming directivity. An A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> B planar array with equilateral triangle geometry and four microphones, three in the vertices and one in the center, was built. Experimental measurements were performed, obtaining an excellent matching with numerical simulations. Finally, the concept of an array of arrays (meta-array) is presented, designed by combining several triangular units and analyzed through numerical simulations.

Signal and Power Integrity Challenges for High Density System-on-Package

As the increasing desire for more compact, portable devices outpaces Moore’s law, innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself, as the case for system-on-package (SoP), has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining, let alone improving, reliability and performance. The fundamental signal, power, and thermal integrity issues are discussed in detail, along with published techniques from around the industry to mitigate these issues in SoP applications.

Segmentation Method for Modeling Heterogeneous Components to Suppress Broadband Simultaneous Switching Noise on a Multilayer Structure

Due to the rapid development of semiconductor manufacturing processes and 5G mobile system design, the need for high-speed digital electronic circuit miniaturization, high operating frequency, and high-speed transmission of data continues to increase. Electronic components are becoming smaller with faster operating speed. Fabricating a complete electronic circuit system with components from different manufacturers is likely to lead to unpredictable electromagnetic interference, signal integrity, power integrity, and other issues. Therefore, electromagnetic compatibility has become a key topic in the design of electronic circuits. We present a modeling approach that can be used to build the stopband and passband in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Z$ </tex-math></inline-formula> -shape and the electromagnetic band gap (EBG) individually. In the model, the printed circuit board (PCB) is divided into five segments of different sizes, each of which has separate rectangular power and ground planes. Through the mushroom-type EBG, these structures are connected as part of a vertical blind hole; that is, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Z$ </tex-math></inline-formula> -shaped power bus comprises a rectangular resonant cavity and transmission line. The proposed modeling method is proven to have accurate simulation, and it can be applied to complicated broadband structure for integrating the whole derivation process into computer programs. The proposed titanic broadband suppression structure can better suppress simultaneous switching noise (SSN) coupling ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\le -30$ </tex-math></inline-formula> dB) within the range of 5 MHz–40 GHz.

Quality of Signal Improvement in Prominent CNTFET Based Ternary Logic System for Futuristic Dielectric Inserted MLGNRs for Integrated Circuit Designs

Booming VLSI technology has graciously facilitated down-scaling dimensions of on-chip devices and interconnects in integrated circuits (ICs) to nano-miniaturized scale. However, at nano-dimensions where added benefits of scaling are constrained by associated highly-dense on-chip nano-interconnect structures, their electro-migration effects and several limiting signal-integrity issues. These cumulatively affect the quality of signal (QoS) at output. Improving output QoS is essential for attaining faithful system performance. The present paper judiciously attempts to address as well as limit this graving issue and is successfully proven by obtained results. Firstly, different structures and their performance of futuristic graphene based multi-layer graphene nano ribbon (MLGNR) interconnect is investigated. These include basic MLGNR and dielectric inserted side contact MLGNR (DS-MLGNR). Secondly, to improve data rates and performance, efficient and novel carbon nanotube field effect transistors (CNTFETs) based ternary logic system is incorporated for the prominent nano-MLGNR interconnects. Thirdly, QoS enhancement of highly potential DS-MLGNR interconnect is proposed using active shielding technique. Finally, is chase to further enrich QoS, adaptive least mean square (LMS) equalization technique is used at the receiver. The proposed work comprising of futuristic novel graphene interconnects with efficient ternary logic system together with adaption of several QoS improvement techniques are magnificent and panacea solution to limiting nano-interconnects in advanced ICs. Several interesting and seminal analyses such as delay, power, power-delay product, crosstalk, eye-diagram are performed that supports the novelty and effectiveness of the proposed work. The vivid performance analyses have been implemented at nano-size 10 nm technology node.

On circuit developments to enable large scale circuit design while computing with noise

The conventional CMOS scaling trend faces device scaling limitations, interconnect bottleneck, and signal integrity issues due to crosstalk, which is the unwanted interference of signals between neighboring metal lines. Traditional computing circuits always try to reduce the crosstalk noise by applying various circuit and layout techniques. In contrast, Crosstalk computing is a new computing framework that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. In this paper, we present a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model for large-scale design. It also performs a comparison study between Crosstalk circuits and existing CMOS-based approaches. The ability to design a wide range of logic circuits (basic and complex logics) and programmable gates compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation results designed at 7 nm show 3.4x improvement density, 62% reduction in Energy-Delay-Product (EDP), and 34.5% improvement in performance compared to counterpart implementation in CMOS circuit style.

Reinforcement-Learning-Based Signal Integrity Optimization and Analysis of a Scalable 3-D X-Point Array Structure

In this article, we, for the first time, propose a reinforcement learning (RL) model to design an optimal 3-D cross-point (X-Point) array structure considering signal integrity issues. The interconnection design problem is modeled to the Markov decision process (MDP). The proposed RL model designs the 3-D X-Point array structure based on three reward factors: the number of bits, the crosstalk, and the IR drop. We applied multilayer perceptron (MLP) and long short-term memory (LSTM) to parameterize the policy. Proximal policy optimization (PPO) is used to optimize the parameters to train the policy. The reward of the proposed RL model is well-converged with variations in the array structure size and hyperparameters of the reward factors. We verified the scalability and sensitivity of the proposed RL model. With the optimal 3-D X-Point array structure design, we analyzed the reward factor and signal integrity issues. The optimal design of the 3-D X-Point array structure shows 17&#x0025;&#x2013;26.5&#x0025; better signal integrity performance than the conventional design in finer process technology. In addition, we suggest a range of possible directions for improvement of the proposed model with variations in MDP tuples, reward factors, and learning algorithms, among other factors. Using the proposed model, we can easily design an optimal 3-D X-Point array structure with a certain size, performance capabilities, and specifications based on reward factors and hyperparameters.

Vibration Signal Integrity Issues and a Novel Detection Method Using One-Class Support Vector Machine

Vibration Signal Integrity Issues and a Novel Detection Method Using One-Class Support Vector Machine

Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits

The presence of RLC line parasitics in a flexible hybrid electronic assembly can lead to signal integrity issues, and their progression over time can lead to catastrophic failures. A technique for extracting the RLC line parasitics from a flexible hybrid electronics assembly is presented. The proposed extraction method exploits the on-chip ESD protection circuits of an IC chip to extract the parasitics of the printed conductors bonded to the chip. This is performed through a single test access port, i.e., two test points. While the parasitics LC are extractable through one-port reflection-based techniques such as time domain reflectometry; the parasitic R requires a two-port measurement such as Kelvin test, which is extremely difficult to perform for printed conductors bonded to small surface-mount IC package devices. The accuracy of the extracted RLC parameters with the proposed method are verified with a prototype developed on a rigid FR4 substrate. Subsequently, the proposed technique is utilized to track the variation of the RLC parasitics for prototypes developed on Kapton Polyimide substrate subjected to different forms of bending.

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Due to advancements in device scaling in very-large-scale integration (VLSI) technology, signal integrity (SI) issues play a major role to determining the performance of on-chip interconnects in high-speed digital circuits. The main SI issues are delays, peak voltage noise effects, crosstalk, and timing uncertainties. Here, the SI issues of the coupled multi-walled carbon nanotube (MWCNT) on-chip interconnects are evaluated with and without the effect of shielding technique and compared to the copper interconnects. The MWCNT exhibits an average of 47.9% smaller propagation delays than Cu in dynamic crosstalk conditions. Further, for crosstalk reduction, the active shielding (AS) and passive shielding (PS) techniques are proposed. With the AS and PS techniques, the MWCNT interconnects experience a decreased delay by 46.8% and 30.15% compared to without shielding technique, respectively. Moreover, the AS exhibits smaller crosstalk effects than the PS technique due to its input switching activities on shielded lines. In addition, the quality of the signal (QoS) and Intersymbol interference (ISI) noise effects of coupled MWCNT interconnect with and without shielding is evaluated. Finally, to improve the QoS and reduce the ISI effects, the decision feedback equalizer with the least mean square adaptive algorithm is implemented at the receiver end.

Modeling and Optimization Design of Signal Interconnect Channel Considering Signal Integrity in Three Dimensional Integrated Circuits

The signal integrity (SI) analysis of a high-speed signal interconnect channel composed of through silicon vias (TSVs) and horizontal re-distribution layers (RDL) is carried out, and the problems of SI, such as transmission loss, crosstalk and coupling effect in the transmission channel, are analyzed and studied. These signal integrity issues are considered in this paper, a signal interconnect channel model is proposed and the equivalent circuit model is deduced as well. Compared with the traditional one, this interconnect channel model has better performance in SI. Further sweep frequency analysis is carried out for different material parameters to achieve signal transmission performance optimization aimed at this model. Test samples of the proposed signal interconnect channel model are designed and fabricated according to the process index, and measured to verify the actual transmission performance. The design and optimization rule of high-speed signal interconnect channel are summarized which proved that the proposed structure has more advantages in signal transmission performance, and has important guiding significance for practical design.

The mitigation of signal integrity issues in coupled MWCNT bundles and a comparison with Cu interconnects

In the nanoscale regime, carbon nanotubes (CNTs) are being considered as a future alternative interconnect material for traditional copper (Cu) wires in integrated circuit technology. The advances in device scaling and the continuous increase of clock frequencies in very large-scale integration technology have resulted in signal integrity (SI) issues. The reduction of such SI issues in coupled multiwalled CNT bundle interconnects is evaluated herein. The worst-case crosstalk delay and peak noise voltage are simulated for three-line coupled interconnects at the 22-nm technology node. To minimize the crosstalk effects, a passive shielding technique is proposed, resulting in reductions of 15.3% and 40.8% in the dynamic in-phase and out-phase crosstalk condition, respectively. The SI of single- and two-line coupled MWCNT bundle interconnects is also investigated based on eye diagrams in a channel simulator and compared with that of Cu interconnects. The eye-opening height is significantly enhanced in the MWCNT bundle and Cu interconnects when using the proposed technique. Moreover, the MWCNT bundle has a higher eye-opening compared with its Cu counterpart.

Study on Power Integrity and Signal Integrity Issues

High frequency channel loss, reflection, and crosstalk are causing degradation of the receiver eye opening, jitter performance, and bit error rate. The voltage drop and current density wisely affects the performance of the PCB.The increase in current density in turn increases the temperature of the board which might cause fault in performance or even explosion of the device. In addition, improper PCB design can lead to noncompliance with EMC regulations. The physical design changes required to meet the use case conditions negatively impact the signal and power integrity performance, limiting the speeds and capabilities that are achievable. The signal and power integrity desires directly oppose one another, so a holistic platform design approach is required to optimize system performance. Since power integrity affects the entire device, from the chip to the chip package to the board to the entire system, a variety of factors must be considered to ensure the design.

Effect of Microwave Absorbing Material on the Straight-Through Performance of Millimetre Wave Coaxial Attenuator

This paper takes the attenuation unit of the millimetre wave coaxial attenuator working in the through state as the research object. The 3D model of the attenuation unit was created. The insertion loss and the VSWR of the attenuation unit were simulated with the help of the HFSS software. The consequences of signal integrity issues were analysed with transmission line theory. The insert loss and VSWR of attenuation unit were simulated by adding a ferrite microwave absorbing material to the model and the thickness of the absorbing material is taken as a variable at different thickness. The relationship between the insertion loss and the VSWR and the thickness of the absorbing material are fitted by numerical fitting and the thicknesses of the absorbing material which optimizes the insertion loss and the VSWR are obtained respectively.

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

&lt;p&gt;The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.&lt;/p&gt;

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

&lt;p&gt;The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.&lt;/p&gt;