Signal Integrity Issues Research Articles

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

Signal Integrity and Power Integrity Issues at System Level

System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity violation, stability, causality, and interoperability, are also discussed.

Power and signal integrity co-design for quad flat non-lead package

The co-design of power and signal integrity issues on a quad flat non-lead (QFN) package is described. A novel decoupling capacitor is achieved by separating the die pad and footprint, coating a solder mask on the footprint and connecting the footprint to the printed circuit board power plane through a via. Large capacitance between power (footprint) and ground (die pad) resulted from the thin mask and large die pad lowering the input impedance of the power delivery network without parasitic effects at low frequency. A power bridge and a ground bridge are introduced to substitute the wire bond to decrease the inductance and hence the impedance magnitude up to 30%, thus enhancing the power integrity at high frequency. A modified design called hybrid power/ground exhibits great signal integrity by providing good reference for signals. The thermal dissipation is also better than the first design through direct contact of the die pad and the footprint ground regions. The overall design demonstrates excellent broadband performance for signal and power integrity.

Aggravated Electromigration of Copper Interconnection Lines in ULSI Devices Due to Crosstalk Noise

In this paper, the impact of crosstalk noise between two adjacent interconnection lines, namely, the aggressor and a victim line, upon electromigration (EM) and Joule-heating failure mechanisms in ULSI microchips has been studied. It was shown that the crosstalk noise leads to distortions of signal waveforms at the far end of the victim line, i.e., the signals supplied to the input of a far-end CMOS inverter. As a result, the shape of the inverter's currents, flowing through the next-stage line (i.e., the line that loads this inverter), is modified in such a way that both EM and Joule heating of the next-stage line are aggravated. The studies reveal that the most deleterious scenario of the crosstalk noise is when the victim and aggressor are switching in opposite directions and the aggressor begins to switch around the trip point of the victim's far-end CMOS inverter (i.e., when both nMOSFET and pMOSFET are open and in a triode mode). Thereby, the crosstalk noise is not only a signal integrity issue as it has been traditionally regarded but also a serious reliability concern that should be taken into account in corresponding reliability models.

Electromagnetic compatibility aware design and testing of intermodulation distortion under multiple co-located sources illumination

Current electromagnetic immunity tests mainly rely on single-frequency sources. However, the evolution of electronic systems leads to miniaturisation and low-cost solutions, in which filters are omitted in front of active non-linear components, also for efficiency reasons. As a result, intermodulation products may leak into the band of operation. The authors propose a comprehensive strategy consisting of design and test methodologies to evaluate in-the-band leakage of out-of-band undesired components, using multiple-tone excitation and relying on an anechoic chamber as test facility. The aim of this study is to demonstrate that an anechoic chamber together with a dual-source network analyser represents an optimal facility to investigate signal integrity issues owing to leakage of intermodulation products.

Crosstalk Simulation Based on Full Wave S-Parameter Extraction Method between High-Speed Signals

Crosstalk between high speed parallel bus signals is one of the most important signal integrity(SI) issues. In this article, a crosstalk simulation method based on full-wave scattering parameters extraction for transmission lines is researched. First, the coupling mechanism between transmission lines is analyzed using S-Parameter network theory and a fast frequency-domain method for crosstalk calculation is introduced. Then based on this method, some basic rules of crosstalk are studied in details and the method is validated by simulation results which agree well with those of RLGC model. At the end of this paper, a practical crosstalk simulation example between high speed data bus signals on a 8-layered printed circuit board is demonstrated step by step.

Low-k Dielectric- A Potential Solution for Crosstalk Induced Signal Integrity issues in SWCNT Interconnects

Crosstalk creates signal integrity issues due to capacitive coupling between adjacent interconnect wires and it is a matter of concern in high frequency interconnects. The reported work on crosstalk induced signal integrity issues in CNT interconnects till date were assuming the value of coupling capacitance as equivalent to the coupling effect between metal interconnects of same dimensions. This work tries to fill that gap; by analyzing crosstalk in bundled SWCNTs with a better model for extracting inter bundle real life coupling capacitances. This work also proposes a novel idea of reducing crosstalk effects by using low-k dielectric materials as isolation between adjacent nets. It is found that compact bundles separated by low-k dielectric can reduce crosstalk effect considerably. Keywords - Crosstalk, signal integrity, SWCNT, MWCNT, Mixed CNT

Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link

Differential signaling has been widely used in high-speed interconnects. Signal integrity issues, such as inter-symbol interference (ISI) and crosstalk between the differential pair, however, still cause significant timing jitter and amplitude noise and heavily limit the performance of the differential link. The pre-emphasis filter is commonly used to reduce ISI but may potentially change the crosstalk behavior. In this paper, we first propose formula-based jitter and noise models considering the combined effect of ISI, crosstalk, and pre-emphasis filter. With the same set of input patterns, experiment shows our models achieve within 5% difference compared with SPICE simulation. By utilizing these formula-based models, we then develop algorithms to directly find out the input patterns for worst-case jitter and worst-case amplitude noise through pseudo-Boolean optimization (PBO) and mathematical programming. In addition, a heuristic algorithm is proposed to further reduce runtime. Experiments show our algorithms obtain more reliable worst-case jitter and noise compared with pseudorandom bit sequences simulation and, meanwhile, reduce runtime by 25× when using a general PBO solver and by 150× when using our proposed heuristic algorithm.

Networks‐on‐Chip: Architectures, Design Methodologies, and Case Studies

As the density of VLSI design increases, more processors or cores can be placed on a single chip. Therefore, the design of a Multi-Processor System-on-Chip (MP-SoC) architecture, which demands high throughput, low latency, and reliable global communication services, cannot be done by just using current bus-based on-chip communication infrastructures. Networks-on-Chip (NoC) has been proposed in recent years as a promising solution of on-chip interconnection network to provide better scalability, performance, and modularity for current and future MP-SoC architectures. The paper entitled “Networks on chips: structure and design methodologies” introduces several NoC architectures and discusses the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Then, a novel Bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is presented, which can break the performance bottleneck caused by bandwidth restriction in conventional NoCs. Since buffers in on-chip networks constitute a significant proportion of the power consumption and the area of interconnects, reducing the buffer size is an important problem. The paper entitled “A buffer sizing algorithm for network on chips with multiple voltage-frequency islands” describes a two-phase algorithm to size the switch buffers in NoC in considering the support of multiple-frequency islands. The paper entitled “Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks” depicts the design of an energy-efficient and reliable channel for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. Among the NoC components, links that connect the NoC routers are the most power-hungry components. The paper entitled “Intelligent on/off dynamic linkmanagement for onchip networks” presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status, where links are turned off and on via the use of a small and scalable neural network. Monitoring and diagnostic systems are required in modern NoC implementations to assure high performance and reliability. In the paper entitled “Status data and communication aspects in dynamically clustered network-onchip monitoring,” the design of a dynamically clustered NoC monitoring structure for traffic and fault monitoring is illustrated. Since biological organisms have better adaptability than computer systems in dealing with environmental changes or noise. A case study on the design of an evolvable neuromolecular hardware motivated from some biological evidence, which integrates interand intra-neuronal information processing, is depicted in the paper entitled “A hardware design of neuromolecular network with enhanced resolvability: a bio-inspired approach.”

Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications

Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integrity issue in integrated circuits operating at Giga-Hertz (GHz) frequencies. In this paper, we propose a method to reduce such via induced signal reflections in on-chip global interconnect lines. We show that the impedance matching can be achieved by the inclusion of an appropriate capacitive load at the junction of the on-chip interconnect line and via. Expressions to determine the capacitance value to be added at via-interconnect junction is derived. Simulation results show that the signal refection is reduced to less than -10 dB in the frequency range of 1 GHz to 10 GHz using the proposed method in 65 nm technology. Proposed method is tested for two types of models - (i) Two interconnect layers connected through a single via and (ii) Two interconnect layers connected from layer 6 to layer 1 through five vias.

Scalable compact models for fast design optimization of complex electromagnetic systems

ABSTRACT: We propose a new parametric macromodeling technique for complex electro-magnetic (EM) systems described by scattering parameters, which are parameterized bymultiple design variables such as layout or substrate feature. The proposed technique isbased on an efficient and reliable combination of rational identification, a procedure to findscaling and frequency shifting system coefficients, and positive interpolation schemes. Para-metric macromodels can be used for efficient and accurate design space explorationand optimization. A design optimization example for a complex EM system is used tovalidate the proposed parametric macromodeling technique in a practical design processflow. V C 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE 00:000–000, 2011. Keywords: parametric macromodeling; rational approximation; interpolation; design optimiza-tion; complex systems I. INTRODUCTION Robust computer-aided design flows are essential for theminimization of signal integrity and electromagnetic (EM)compatibility issues in the development of modern digitaland mixed-signal systems [1–5]. Chip packages, data bus-ses, connectors, and cables require to be properlydesigned, since from the early design stage, they can seri-ously limit transmission data rates or increase the bit errorrate beyond acceptable limits. In order to avoid theseproblems, design space exploration, design optimization,and sensitivity analysis are usually performed by multiplefrequency-domain simulations for different design parame-ter values (e.g., layout features), trying to meet govern-ment regulations and customer requirements. In this per-spective, parametric (scalable) macromodels are wellsuited to efficiently and accurately perform these designactivities, while using multiple EM simulations is oftenhigh computationally expensive due to the high computa-tional cost per simulation. Parametric macromodels aremultivariate models that capture the complex behavior ofEM systems, which is typically characterized by the fre-quency (or time) and several design parameters, such aslayout or substrate features.Over the last years, several different parametric macro-modeling techniques have been developed. In [6, 7], bothpoles and residues are parameterized, and it results inaccurately modeling dynamic multivariate data. Overallstability and passivity of parametric macromodels are notguaranteed. Recently, some parametric macromodelingtechniques able to guarantee overall stability and passivityof parametric macromodels have been proposed [8–11].The techniques described in [8, 9] are based on the pas-sive interpolation of a set of stable and passive univariatemacromodels, called root macromodels, treated as input–output systems. This interpolation process of input–outputsystems leads to parameterize only the residues. A passiveinterpolation of the state-space matrices of a set of rootmacromodels is proposed in [10, 11], which provides anincreased modeling capability with respect to [8, 9] due tothe parameterization of both poles and residues. Unfortu-nately, these methods are sensitive to some issues relatedto the interpolation of state-space matrices [12] and can

Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects

As technology shrinks, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise (PSN) plays a greater role in sub-100 nm technologies and creates signal integrity issues. It is vital to consider supply voltage noise effects: 1) during design validation to apply sufficient guardbands to critical paths, and 2) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure is proposed to maximize PSN effects on critical paths considering the impact of local voltage drop. The proposed pattern generation and validation flow is implemented on the ITC'99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed on the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practised in industry.

Networks on Chips: Structure and Design Methodologies

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires high‐performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on‐chip bus or multilayer bus architecture. With the advent of many‐core architectures, the bus architecture becomes the performance bottleneck of the on‐chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on‐chip communication infrastructure, which is commonly considered as an aggressive long‐term approach for on‐chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self‐reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

Latency Insertion Method (LIM) for DC Analysis of Power Supply Networks

Process scaling in modern integrated circuits has led to multiple signal and power integrity issues. In particular, ensuring reliable performance of on-chip power delivery systems has become a major design challenge. Rigorous analysis and simulations are required at the design stage to ensure proper functionality of an on-chip power supply. This puts a strain on existing numerical tools due to the sheer size of the power grids. In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network. The proposed method is shown to be very efficient for modeling of networks with very large numbers of nodes. The comparison with one of the well-established methods used for the power grid analysis today, the Random-Walk algorithm, shows that LIM is almost two orders of magnitude faster.

Inductive Network Model for the Radiation Analysis of Electrically Small Parallel-Plate Structures

Vertical interconnections between parallel-plate structures as often encountered in electronic designs are the source of various signal integrity and radiated-emission issues. The presented analysis is based on a coupled multiport equivalent-circuit model for frequencies below the first cavity resonance. A main subject is the determination of the self- and mutual port inductances, for which exact closed-form expressions are presented. For special port positions simple approximate formulas are derived. The results show that the considered structure is inherently resonant. The resonance frequency depends on the number and configuration of the ground interconnections and can be estimated from the equivalent circuit. The radiated emission of the whole structure is determined by the capacitive current in the network model, based on a simple Hertzian-dipole radiation characteristic. The model is validated by numerical 3-D field simulations and measurements.

A Novel Compact Electromagnetic Bandgap Structure in Power Plane for Wideband Noise Suppression and Low Radiation

A compact reduced unit cell size electromagnetic bandgap (EBG) power plane, realized with a combination of alternating impedance EBG and multiple narrow slits, is presented. By concatenating 2 × 2 high-frequency unit cells, a virtual low-frequency EBG unit cell is synthesized without changing the overall dimensions. In this configuration, the basic slit in the high-frequency unit cell remained same, and an additional slit with longer dimensions is added in parallel to the basic slit by synthesizing a larger low-frequency unit cell. EBG is characterized for its dispersion diagram, noise suppression, signal integrity, and electromagnetic radiation. Fabricated EBG exhibits a bandgap from 0.9 to 3.5 GHz with isolation better than -40 dB over the band. Radiated emission of the new EBG is small with an average value of 35 dB·uV/m. Compact EBG also exhibits low impedance, which is less than 1 Ω over the stopband. Eye patterns are generated to analyze signal integrity issues when the data lines are referenced over the solid ground plane and EBG plane. The degradation of the maximum eye opening and the maximum eye width for the proposed EBG power plane at 2 Gb/s data rate is about 17.8% and 1%, respectively, with reference to the equivalent board with solid power plane.

Enhancing Signal and Power Integrity Using Double Sided Silicon Interposer

A novel double sided silicon interposer for low impedance power delivery is presented. In this letter, a model for power ground planes in inhomogeneous dielectrics with conductive subsections using the multi-layered finite difference method (M-FDM) is presented. Benefits of the silicon interposer in mitigating signal integrity issues arising due to return path discontinuities (RPDs) are also discussed for the first time along with a comparison to glass interposer.

Time and Laplace‐domain methods for MTL transient and sensitivity analysis

PurposeThe purpose of this paper is to present the development and comparison of selected time‐domain and Laplace‐domain methods for the simulation of waves propagating along multiconductor transmission lines (MTLs), both uniform and nonuniform, and sensitivities with respect to distributed and lumped parameters of MTL systems.Design/methodology/approachA methodology is based on discrete, semidiscrete and continuous MTL models formulated and solved both in the time and Laplace domains, latter combined with a numerical inverse Laplace transform (NILT).FindingsThe most accurate method is that based on the MTL Laplace‐domain continuous model, processed via the MTL chain matrix and connected with an NILT. This method concurrently shows minimal RAM requirements, and in case of uniform MTLs, it runs fastest. For nonuniform MTLs, however, the implicit Wendroff formula is fastest, as long as the RAM is available.Research limitations/implicationsThe research is limited to linear MTLs only and the methods suppose terminating circuits based on their generalized Thévenin equivalents. They can be, however, generalized for more complex systems via more sophisticated boundary conditions treatment. The time‐domain methods have further potential to be generalized towards nonlinear MTLs.Practical implicationsThe methods considered can contribute to solving signal integrity issues in high‐speed electronic systems, the Matlab routines developed can serve in education process as well.Originality/valueThe implicit Wendroff formula has been adapted to enable simulation of voltage and/or current distributions and their sensitivities along the nonuniform MTLs' wires. Besides, semidiscrete and continuous nonuniform MTL models have been elaborated to enable sensitivities determination, both in the time and Laplace domains, latter connected with the NILT technique based on fast Fourier transform/inverse fast Fourier transform and quotient‐difference algorithms.

Decoder-Type Gate Driver Circuits Fabricated with Amorphous Silicon Thin-Film Transistors for Active Matrix Displays

This paper quantitatively analyzes the signal integrity and device stability issues of gate driver circuits for active matrix displays integrated with hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), and reveals that the clock-coupling noises and threshold voltage shift due to the DC gate bias in previous gate driver circuits can seriously affect the image quality. To resolve these problems, two types of decoder-based gate driver circuits have been proposed, that can completely avoid the floating output node to prevent the clock-coupling noises without applying the DC gate bias to all the TFTs used in the gate driver circuits. The performances and characteristics of the two proposed types of gate drivers will be discussed and compared, and the experimental results for the fabricated circuits will be presented.

Decoder-Type Gate Driver Circuits Fabricated with Amorphous Silicon Thin-Film Transistors for Active Matrix Displays

This paper quantitatively analyzes the signal integrity and device stability issues of gate driver circuits for active matrix displays integrated with hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), and reveals that the clock-coupling noises and threshold voltage shift due to the DC gate bias in previous gate driver circuits can seriously affect the image quality. To resolve these problems, two types of decoder-based gate driver circuits have been proposed, that can completely avoid the floating output node to prevent the clock-coupling noises without applying the DC gate bias to all the TFTs used in the gate driver circuits. The performances and characteristics of the two proposed types of gate drivers will be discussed and compared, and the experimental results for the fabricated circuits will be presented.