Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits

Abstract

The presence of RLC line parasitics in a flexible hybrid electronic assembly can lead to signal integrity issues, and their progression over time can lead to catastrophic failures. A technique for extracting the RLC line parasitics from a flexible hybrid electronics assembly is presented. The proposed extraction method exploits the on-chip ESD protection circuits of an IC chip to extract the parasitics of the printed conductors bonded to the chip. This is performed through a single test access port, i.e., two test points. While the parasitics LC are extractable through one-port reflection-based techniques such as time domain reflectometry; the parasitic R requires a two-port measurement such as Kelvin test, which is extremely difficult to perform for printed conductors bonded to small surface-mount IC package devices. The accuracy of the extracted RLC parameters with the proposed method are verified with a prototype developed on a rigid FR4 substrate. Subsequently, the proposed technique is utilized to track the variation of the RLC parasitics for prototypes developed on Kapton Polyimide substrate subjected to different forms of bending.