SiGe Substrates Research Articles

Electronic and structural characteristics of Zr-incorporated Gd2O3 films on strained SiGe substrates

Zr-incorporated Gd(2)O(3) films were grown on various substrates as a function of Zr content. The extent of interfacial reactions was found to be critically dependent on both the incorporated Zr content and the substrate type. Specifically, the silicide layer was suppressed and the Gd(2)O(3) phase was changed to ZrO(2) on a Si substrate with increasing Zr content. Crystalline Gd(2)Ge(2)O(7) was grown on a Ge substrate, as the result of interfacial reactions between Gd-oxide and the Ge substrate. However, interfacial reactions were not affected by the amount of Zr incorporated. On the SiGe/Si substrate, reactions between Gd-oxide and Si could be controlled effectively by the incorporation of Zr, while the extent of reactions with Ge was significantly enhanced as the Zr content increased. The formation of an interfacial layer between the film and the SiGe substrate resulted in a textured crystalline growth.

Evaluation of super-critical thickness strained-Si on insulator (sc-SSOI) substrate

Crystal quality and strain distribution in SOI layer of conventional strained-Si on insulator (SSOI) and super-critical thickness strained-Si on insulator (sc-SSOI) were evaluated by in-plane X-ray diffraction (XRD), Raman spectroscopy, and other techniques. The surface defect distribution measured by wafer inspection system shows pit-type and line defects in both SSOI layers. More specifically, the sc-SSOI material has more line defects than conventional SSOI layers. Cross-hatched pattern defects were observed using X-ray topography (XRT) measurements. Raman mapping of 300 mm wafers shows the strain at the center of the wafer is larger than at the edge. In magnified close-up mapping, cross-hatched contrasts corresponding to misfit dislocations are observed, while the surface morphology is completely smoothed out. In-plane XRD measurements show the strain depth variations are quite uniform along the depth direction. The full width at half maximum (FWHM) of in-plane XRD peaks obtained from strained-Si layers is much larger than for un-strained SOI and bulk Si, reflecting poor crystal quality. SSOI was fabricated by the layer transfer of strained-Si on a virtual SiGe substrate. Therefore, we believe the crystal quality and strain distribution originate in the donor strained Si when virtual SiGe substrate is the starting material.

Observation of Crystalline Imperfections in Supercritical Thickness Strained Silicon on Insulator Wafers by Synchrotron X-ray Topography

A commercial supercritical thickness strained Si-on-insulator (SC-sSOI) wafer was characterized by large-area synchrotron x-ray topography at the glancing incident condition. Several kinds of contrast showing crystalline imperfections were observed all over the wafers, such as macule and crosshatch patterns. Similar crosshatch patterns were also observed in the x-ray topographs of a conventional strained Si-on-insulator (sSOI) wafer and a strained Si wafer that has the strained Si layer epitaxially grown on the relaxed SiGe layer on the insulator (SGOI) structure. This indicates that the crosshatch pattern of the SC-sSOI wafer originates from the lattice distortion in the original SiGe substrate of the strained Si layer.

Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device

The effects of a strained silicon layer on the thermal stability of nickel (germano)silicide for nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET) devices are discussed in this study. Three different thicknesses, 5, 13, and 40 nm, of silicon layers on silicon germanium (SiGe) were prepared for this experiment. The effects of the silicidation rapid thermal annealing (RTA) temperature and postsilicidation annealing temperature for the different silicon layer thicknesses were studied. For comparison, a bulk silicon substrate and a SiGe substrate were also used. Silicides with the thin strained silicon layers (5 and 13 nm) on SiGe showed good thermal stability in this study. However, the other silicides using bulk silicon, 40-nm-thick silicon on SiGe, and the SiGe substrate underwent degradation due to silicide agglomeration during annealing. A SiO2 layer was found on the silicide using the SiGe substrate. In this study, several analysis methods such as four-point probe measurement, field-emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), and Auger electron spectroscopy (AES) were used for detailed study.

Strain engineered Si∕SiGe resonant interband tunneling diodes with outside barriers grown on Si0.8Ge0.2 virtual substrates

Si-based resonant interband tunneling diodes (RITDs) grown on commercially available Si0.8Ge0.2 virtual substrates were studied. Peak-to-valley current ratios (PVCRs) were improved by utilizing strain induced band offsets to 3.5 with a peak current density (Jp) of 161A∕cm2. More specifically, a tensilely strained Si layer on the p-side and a compressively strained Si0.5Ge0.5 layer on the n-side were added to the design to form enhanced potential barriers away from the tunneling junction. The outside barriers deepen the respective hole and electron quantum wells and also block nonresonant tunneling current, which improved the PVCR significantly. However, due to the large surface roughness of the SiGe virtual substrates used in this study, the RITDs grown on Si0.8Ge0.2 substrates exhibit a smaller PVCR overall than RITDs optimized on standard Si substrates. Better performance is expected by using higher quality SiGe substrates with smaller surface roughness.

Stepwise Ni-silicide Process for Parasitic Resistance Reduction for Silicon/metal Contact Junction

The parasitic resistance is studied to silicon/metal contact junction for improving device performance and to lower contact/serial resistance silicide in natural sequence. In this paper constructs the stepwise Ni silicide process for parasitic resistance reduction for silicon/metal contact junction. We have investigated multi-step Ni silicide on SiGe substrate with stepwise annealing method as an alternative to compose more thermally reliable Ni silicide layer. Stepwise annealing for silicide formation is exposed to heating environment with <TEX>$5^{\circ}C/sec$</TEX> for 10 seconds and a dwelling for both 10 and 30 seconds, and ramping-up and the dwelling was repeated until the final annealing temperature of <TEX>$700\;^{\circ}C$</TEX> is achieved. Finally a direct comparison for single step and stepwise annealing process is obtained for 20 nm nickel silicide through stepwise annealing is <TEX>$5.64\;{\Omega}/square$</TEX> at <TEX>$600\;^{\circ}C$</TEX>, and it is 42 % lower than that of as nickel sputtered. The proposed stepwise annealing for Ni silicidation can provide the least amount of NiSi at the interface of nickel silicide and silicon, and it provides lower resistance, higher thermal-stability, and superior morphology than other thermal treatment.

Ab-initio study on indium diffusion in silicon substrate under hydrostatic stress

In this paper, we report our ab-initio study on indium diffusion in strained Si. We investigated the minimum energy path as well as the migration energy for indium atoms in the hydrostatic strained silicon wherein the strain was incorporated by constructing a silicon layer on SiGe substrate with 20% germanium mole fraction. The ab-initio calculation allowed us to figure out the lowest-energy structure (InS+Sii Td) and the next lowest energy structure (Ini Td) during indium diffusion. The energy of migration barrier was also predicted from the nudged elastic band and climbing nudged elastic band method. Consequently, we found that the energy barrier was a little higher than the case of unstrained Si.

Laser-Induced Melt-Mediated Ni(Pt) Germanosilicide Formation on Condensed Si[sub 1−x]Ge[sub x]/Si Substrates

dInstitute of Microelectronics, Singapore 117685 e Singapore Institute of Manufacturing Technology (SIMTech), Singapore 638075 Laser-induced melt-mediated Ni-based germanosilicide has been formed on condensed SiGe substrates with 40% Ge. Pure Ni germanosilicide formation was plagued by the presence of amorphous oxygen-rich globules. Platinum alloying has greatly improved the morphology of the laser-induced NiPt germanosilicide with the alleviation of oxygen incorporation during laser annealing. This results in an improvement in the surface roughness and electrical conductivity of the germanosilicide film. Low affinity of Pt toward oxygen is believed to have resulted in this improvement.

On the electron mobility enhancement in biaxially strained Si MOSFETs

This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (0 0 1) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger–Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

High-k Gate Stack Formation on Strained SiGe Substrate for MOSFET Applications

In this paper, we examine the high-k gate stack formation on strained SiGe for p-channel MOSFET applications by comparing two different surface passivations. Experimental results show that although both surface nitridation and silicon passivation provide good MOS capacitors on SiGe substrates, the devices with ultra-thin Si passivation layer provides high hole mobility than those with surface nitridation. It is believed that nitrogen incorporation during surface nitrdation may degrade hole mobility.

High-k Gate Stack Formation on Strained SiGe Substrate for MOSFET Applications

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SiGe double barrier resonant tunneling diodes on bulk SiGe substrates with high peak-to-valley current ratio

The authors present high-quality p-type SiGe double barrier resonant tunneling diodes obtained from bulk SiGe substrates grown by the multicomponent zone-melting method and by the layer deposition with molecular beam epitaxy. Devices exhibit a high peak-to-valley current ratio up to 8.8 at 4.2K and a negative differential resistance up to 340K. The result demonstrates that bulk SiGe substrates have a clear potential impact for fabricating high-performance SiGe heterostructure devices based on quantum transport.

Application of Czochralski-grown SiGe bulk crystal as a substrate for luminescent strained quantum wells

Czochralski-grown Si1−xGex bulk crystal (x=0.085) was utilized as a substrate for strained Si-based quantum wells (QWs). The linewidth of the (400) x-ray rocking curve of the SiGe(100) substrate was comparable with that of the Si(100) substrate, and no peak splitting was observed in the line scan all over the substrate. Epitaxial growth of strained QWs designed as a couple of strained Si/strained Ge QWs have been attempted simultaneously on SiGe(100) and Si(100). Photoluminescence measurements revealed that the sample on SiGe(100) exhibits peaks from excitons confined in QWs without any dislocation-related luminescence in contrast to that on Si(100).

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.

NiSi for CMOS: Comparison of Phase Transformation Curves for Si and SiGe Substrates Annealed in a Near-Isothermal Cavity

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Zero Valley Splitting at Zero Magnetic Field for Strained Si/SiGe Quantum Wells

AbstractThe electronic structure for a strained silicon quantum well grown on a tilted SiGe substrate is calculated using an empirical tight-binding method. For a zero substrate tilt angle the two lowest minima of the conduction band define a non-zero valley splitting at the center of the Brillouin zone. A finite tilt angle for the substrate results in displacing the two lowest conduction band minima to finite k0 and -k0 in the Brillouin zone with equal energy. The vanishing of the valley splitting for quantum wells grown on tilted substrates is found to be a direct consequence of the periodicity of the steps at the interfaces between the quantum well and the buffer materials.

Magnetic-field dependence of valley splitting in Si quantum wells grown on tilted SiGe substrates

The valley splitting of the first few Landau levels is calculated as a function of the magnetic field for electrons confined in a strained silicon quantum well grown on a tilted SiGe substrate, using a parameterized tight-binding method. For a zero substrate tilt angle, the valley splitting slightly decreases with increasing magnetic field. In contrast, the valley splitting for a finite substrate tilt angle exhibits a strong and non-monotonous dependence on the magnetic field strength. The valley splitting of the first Landau level shows an exponential increase followed by a slow saturation as the magnetic field strength increases. The valley splitting of the second and third Landau levels shows an oscillatory behavior. The non-monotonous dependence is explained by the phase variation of the Landau level wave function along the washboard-like interface between the tilted quantum well and the buffer material. The phase variation is the direct consequence of the misorientation between the crystal axis and the confinement direction of the quantum well. This result suggests that the magnitude of the valley splitting can be tuned by controlling the Landau-level filling factor through the magnetic field and the doping concentration.

Analysis of Hole Transport in Arbitrarily Strained Germanium

Full-band Monte Carlo simulations are performed to study the properties of hole transport in bulk Germanium under general strain conditions. The band structures are calculated with the empirical non-local pseudopotential method. For Monte Carlo simulations acoustic and optical phonon scattering as well as impact ionization are taken into account. Results for biaxially strained Ge grown on a [001] oriented SiGe substrate and for uniaxial compressive stress in [110] exhibit a high mobility enhancement.

Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100 nm technology nodes.

Surface roughness and interface engineering for gate dielectrics on strained layers

The change in the morphology of various gate dielectrics (including deposited ZrO2 and TiO2) on strained-Si on relaxed SiGe/Si and strained-SiGe layers is studied using an atomic force microscope (AFM). The AFM observation was carried out before and after oxidation. It has been found that the oxidation rate of strained-Si was affected by the existence of the cross-hatch related surface morphology. As a result, the surface roughness increases after oxidation. The roughness increase is more pronounced in a 26% Ge-content samples than in a 9% Ge-content sample. Transmission electron microscopy (TEM) has been used to identify the structure of the deposited layers and their interface with the strained-Si or SiGe substrates. Structural and electrical characterization results for deposited high-k gate dielectrics on strained-Si using Al/ZrO2/n-Si and Al/TiO2/n-Si metal-insulator-semiconductor (MIS) structures with equivalent oxide thickness (EOT) of 2.5 nm are presented. Effects of nitrogen incorporation on the electrical, interfacial, charge trapping and reliability properties of ultrathin oxide/oxynitride films grown using rapid thermal oxidation on strained-SiGe substrates are also discussed.