SiC Trench MOSFET Research Articles

Characterization and Analysis of Degradation for 1.2-kV Rated SiC Trench MOSFETs Under Repetitive Switching Impulses

Characterization and Analysis of Degradation for 1.2-kV Rated SiC Trench MOSFETs Under Repetitive Switching Impulses

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Fabricating and TCAD Optimization for a SiC Trench MOSFET With Tilted P-Shielding Implantation and Integrated TJBS

Fabricating and TCAD Optimization for a SiC Trench MOSFET With Tilted P-Shielding Implantation and Integrated TJBS

Novel SiC Trench MOSFET with Improved Third-Quadrant Performance and Switching Speed.

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (VF) at IS = 100 A/cm2, which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (Emox). Additionally, the gate-drain capacitance (Cgd) and gate-drain charge (Qgd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater Ron,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs

This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (Vth) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as Vth shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.

A Novel 6500 V SiC Trench MOSFET with Integrated Unipolar Diode for Improved Third Quadrant and Switching Characteristics.

A 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation, and reduce switching loss. An N type base region under the trench dummy gate provides a low barrier path to suppress hole injection during the reverse conduction operation. The reverse conduction voltage VON is reduced to 1.11 V, and the reverse recovery charge (QRR) is reduced to 1.22 μC/cm2. The gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) of the UD-MOS are also reduced to improve switching loss due to the thick oxide layer between the trench gate and dummy gate. The proposed device exhibits an excellent loss-related figure of merit (FOM). It provides a high-voltage SiC MOSFET prototype with potential performance advantages for voltage source converter-based high voltage direct current applications.

An Adjustable P-Region Potential SiC Trench MOSFET With Improved High-Frequency and Short-Circuit Performance

An Adjustable P-Region Potential SiC Trench MOSFET With Improved High-Frequency and Short-Circuit Performance

SiC Trench MOSFET with Depletion-Mode pMOS for Enhanced Short-Circuit Capability and Switching Performance

A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (TMOS) with depletion-mode pMOS (D-pMOS) is proposed and investigated via TCAD simulation. It has an auxiliary gate electrode that controls the electrical connections of P-shield layers under the trench bottom through the D-pMOS. In linear operation, the D-pMOS is turned off and then the potential of the P-shield layers is raised with the auxiliary gate, which shrinks the width of the depletion region of the P-shield/N-drift junction to reduce the resistance of the JFET region. In the saturation operation, the saturation current density of the proposed TMOS is reduced, benefiting from its relatively large cell pitch. The design concept eases the tension between specific on-resistance and short circuit capabilities. Numerical simulation results show that the proposed TMOS exhibits a short circuit withstand time that is 1.92 times longer than that of the conventional TMOS. In addition, a drive tactic is introduced and optimized for the proposed TMOS, which requires only one set of gate drivers. Compared with the conventional TMOS, the switching performance is improved and the switching loss is reduced by 40%.

Avalanche ruggedness and failure mode of SiC trench MOSFETs

Avalanche ruggedness of SiC MOSFETs is of interest for many researchers since these devices are used in various applications. Existing inductances in the application circuits are the main reason that SiC MOSFETs may enter into avalanche condition. Under certain avalanche operating conditions, the device failure is inevitable. Avalanche failures of SiC MOSFET are usually classified into current-driven and temperature-driven categories. In this paper single-pulse avalanche behaviour of SiC trench MOSFETs of different voltage classes is experimentally investigated. The measurements were performed under various conditions of current, energy, avalanche time and temperature. To gain a better understanding of device failure and to correlate with the experimental results, 1D thermal simulations were carried out and critical chip temperatures which are expected to cause device failures are shown. Furthermore, repetitive avalanche measurements and parameter analyses are discussed. It is shown that SiC trench MOSFETs of different chip sizes show similar avalanche ruggedness. The critical chip temperatures were found to be similar for devices of all avalanche breakdown voltage classes. No drift of the relevant device parameters has been seen after repetitive avalanche measurements. The method used in this work can be used to predict the avalanche behaviour of SiC trench MOSFETs.

A novel 4H‐SiC accumulation mode MOSFET with ultra‐low specific on‐resistance and improved reverse recovery capability

AbstractA novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device.

Impact of Turn-Off Gate Voltage and Temperature on Threshold Voltage Instability in Pulsed Gate Voltage Stresses of SiC MOSFETs

Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.

A Review of Power Electronic Devices for Heavy Goods Vehicles Electrification: Performance and Reliability

This review explores the performance and reliability of power semiconductor devices required to enable the electrification of heavy goods vehicles (HGVs). HGV electrification can be implemented using (i) batteries charged with ultra-rapid DC charging (350 kW and above); (ii) road electrification with overhead catenaries supplying power through a pantograph to the HGV powertrain; (iii) hydrogen supplying power to the powertrain through a fuel cell; (iv) any combination of the first three technologies. At the heart of the HGV powertrain is the power converter implemented through power semiconductor devices. Given that the HGV powertrain is rated typically between 500 kW and 1 MW, power devices with voltage ratings between 650 V and 1200 V are required for the off-board/on-board charger’s rectifier and DC-DC converter as well as the powertrain DC-AC traction inverter. The power devices available for HGV electrification at 650 V and 1.2 kV levels are SiC planar MOSFETs, SiC Trench MOSFETs, silicon super-junction MOSFETs, SiC Cascode JFETs, GaN HEMTs, GaN Cascode HEMTs and silicon IGBTs. The MOSFETs can be implemented with anti-parallel SiC Schottky diodes or can rely on their body diodes for third quadrant operation. This review examines the various power semiconductor technologies in terms of losses, electrothermal ruggedness under short circuits, avalanche ruggedness, body diode and conduction performance.

A Fully Self-Aligned SiC Trench MOSFET with 0.5 μm Channel Pitch

SiC power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from their theoretical limits of performance. At blocking voltages above 1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and JFET regions. Trench MOSFETs have smaller cell area than planar DMOSFETs, and are inherently more scalable. Both Rohm and Infineon devices have cell pitches of about 3 μm per active channel. In this paper we demonstrate a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs”.

An investigation of avalanche ruggedness and failure mechanisms of 4H SiC trench MOSFETs in unclamped inductive switching by varying load inductances over a wide range

The avalanche ruggedness of unclamped inductive switching of 1.2 kV SiC trench MOSFETs was investigated with load inductances ranging from 1 μH to 5 mH. The SiC trench MOSFETs showed an extremely high avalanche current of more than 6000 A cm−2 at 1 μH, which was 3.3 times higher than state-of-the-art 1.2 kV Si IGBTs. This indicates that modules of SiC trench MOSFETs could show higher ruggedness for parallel connections. In addition, SiC trench diodes in which only the n+ source regions were eliminated from the MOSFETs were fabricated to verify the failure mechanism by the activation of parasitic bipolar transistors. In medium-load inductances from 10 μH to 100 μH, the MOSFETs showed lower avalanche ruggedness than the diodes, and failures were caused by the activation of the parasitic bipolar transistors. For inductances outside that range, the MOSFETs showed identical ruggedness to the diodes, and the failures were caused by the source metals melting.

Numerical demonstration of SiC trench MOSFET with integrated heterojunction diode for enhanced performance

In this paper, a novel SiC trench-gate MOSFET with integrated heterojunction diode (HD-TG-MOS) is proposed and studied according to TCAD simulations. The n-type polysilicon/n-type SiC HD is introduced into the groove by the direct contact between the polysilicon and semiconductor. As a result, significant improvements of device performance in the first and third quadrants are observed as compared to the conventional SiC trench-gate MOSFET (C-TG-MOS). Better yet, aided by the extremely low barrier height across the heterojunction, the knee voltage reduces to only 0.5 V with comparison of that of ∼2.7 V for the body diode, when used for reverse freewheeling. These promotions make SiC HD-TG-MOS more advantageous for HF power conversion applications. In addition, another cell architecture variant adopting a similar concept is presented, and the according process implementation is addressed as well from viewpoint of manufacture.

Simulation Study of a 650V Hybrid-Channel SiC Trench MOSFET with Improved On-State Performance

Simulation Study of a 650V Hybrid-Channel SiC Trench MOSFET with Improved On-State Performance

4H–SiC trench MOSFET with Inverted-T groove

A novel 4H–SiC trench MOSFET with Inverted-T groove (IT-UMOS) is proposed and investigated by numerical TCAD simulations in this paper. The IT-UMOS features an Inverted-T groove beneath the gate trench. As a result, compared with the conventional trench MOSFET (C-UMOS) and step-UMOS, the IT-UMOS boasts a much lower gate-drain charge owing to the introduction of Inverted-T groove, thus a lowest switching loss is attained. In addition, the maximum oxide electric field during the blocking state in IT-UMOS is significantly reduced, which means the breakdown capability is not compromised. The dynamic figure of merit (FOM) Ron,sp × Qgd of IT-UMOS is the lowest among these three structures.

Design of 1.2 kV SiC trench MOSFET using tilted ion implantation for suppression of electric field crowding at the bottom of the gate oxide

In this study, the effect of applying the tilted ion implantation process of a 1.2 kV SiC trench metal–oxide–semiconductor field-effect transistor on the electrical characteristics of the devices was investigated. P-shielding with tilted ion implantation protects both the sidewall and bottom of the trench from an electric field, enabling stable high-voltage operation, and the cell pitch can be reduced by using only one channel. Moreover, the tilted ion implantation process has the advantage of not requiring additional masks. For a comparative analysis, the tilt angle for ion implantation into the trench was changed in a TCAD simulation. A high breakdown voltage of 1617 V was achieved under an optimized tilt angle of 18.2°, and a low on-resistance of 2.9 mΩ cm2 was obtained via structural optimization.

Significant Improvement of Switching Characteristics in a 1.2‐kV SiC SWITCH‐MOS by the Application of Kelvin Source Connection

Here we show, for the first time, a significant improvement of switching characteristics in a 1.2‐kV SiC Schottky barrier diode‐wall integrated trench MOSFET (SWITCH‐MOS) by the application of a Kelvin source (KS) connection. Turn‐on loss (Eon) was greatly reduced, with superior Eon‐dVDS/dt trade‐off characteristics at a moderate dVDS/dt value of about 10 kV/μs, because the SWITCH‐MOS with KS achieves a more suppressed peak reverse recovery current in embedded Schottky barrier diodes even at a higher dID/dt during the turn‐on operation than a state‐of‐the‐art SiC trench MOSFET with KS. This feature is a peculiarity of the SWITCH‐MOS when the KS connection is applied. Notably, measured and calculated results confirmed that the SWITCH‐MOS with KS had less dissipated turn‐off loss, especially in a second half of turn‐off regions (Region 2), than the SWITCH‐MOS w/o KS. However, owing to a higher negative turn‐off dID/dt, the MOSFET with KS has a larger drain surge voltage. With an optimum gate resistance, the SWITCH‐MOS with KS has 8% less total switching loss than a SWITCH‐MOS without KS, and 29% less than a state‐of‐the‐art SiC trench MOSFET with KS, while keeping a moderately low dVDS/dt of 10 kV/μs and suppressing a drain peak voltage of <720 V. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge (Q gd,sp) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage (BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance (R on,sp) becomes smaller. In the end, comparing with the bottom p+ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, BV 2/R on,sp) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is improved by 310%, respectively.