SiC Planar MOSFETs Research Articles

Comparison and analysis on static and dynamic performance of 1.2-kV SiC planar MOSFETs with different cell topologies

1.2-kV SiC MOSFETs with different cell topologies were fabricated based on the same design and process parameters in a commercial 6-inch SiC foundry. A series of comparative evaluations were conducted on the static and dynamic performance of SiC MOSFETs with common linear, island-shaped P+ linear, current sharing linear, and hexagonal cell topologies for the first time. The common linear cell topology has the lowest switching loss, but the highest on-resistance. The island-shaped P+ linear and current sharing linear cell topologies optimized the cell pitch, reduced the specific on-resistance by 9.68 %, but the freewheeling and surge capability of their body diode have been decreased. The current sharing linear cell topology has the highest Ciss/Crss, making it the lowest in crosstalk intensity. The hexagonal cell topology has the lowest on-resistance, but performs the worst in terms of blocking characteristics and switching losses.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

One-Probe Nanoprobing of Power Devices and Electronic Packages

Results involving the use of a single nanoprobing contact are presented, on both a SiC planar MOSFET device, and a small system-in package. In both cases, mechanical polished samples were prepared, and then probed with a single contact. For the SiC MOSFET, the depletion zones were imaged while the samples were mounted on a 45 ° stub. Discussion of the different signals generated from Passive Voltage Contrast (PVC) and Electron Beam Induced Current (EBIC), as well as possible artifacts of sample grounding, are provided. For the package, Electron Beam Absorbed Current (EBAC) provided indication of connected features within the sample. The experiment showed the capability of measuring features across three orders of magnitude in size.

A SiC Planar MOSFET with an Embedded MOS-Channel Diode to Improve Reverse Conduction and Switching.

A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (QGD) of the proposed device is 20 nC/cm2, and the reverse-transfer capacitance (CGD) is 14 pF/cm2, which are lower than the QGD of 230 nC/cm2 and the CGD of 105 pF/cm2 for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained.

Impact of Turn-Off Gate Voltage and Temperature on Threshold Voltage Instability in Pulsed Gate Voltage Stresses of SiC MOSFETs

Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.

A Review of Power Electronic Devices for Heavy Goods Vehicles Electrification: Performance and Reliability

This review explores the performance and reliability of power semiconductor devices required to enable the electrification of heavy goods vehicles (HGVs). HGV electrification can be implemented using (i) batteries charged with ultra-rapid DC charging (350 kW and above); (ii) road electrification with overhead catenaries supplying power through a pantograph to the HGV powertrain; (iii) hydrogen supplying power to the powertrain through a fuel cell; (iv) any combination of the first three technologies. At the heart of the HGV powertrain is the power converter implemented through power semiconductor devices. Given that the HGV powertrain is rated typically between 500 kW and 1 MW, power devices with voltage ratings between 650 V and 1200 V are required for the off-board/on-board charger’s rectifier and DC-DC converter as well as the powertrain DC-AC traction inverter. The power devices available for HGV electrification at 650 V and 1.2 kV levels are SiC planar MOSFETs, SiC Trench MOSFETs, silicon super-junction MOSFETs, SiC Cascode JFETs, GaN HEMTs, GaN Cascode HEMTs and silicon IGBTs. The MOSFETs can be implemented with anti-parallel SiC Schottky diodes or can rely on their body diodes for third quadrant operation. This review examines the various power semiconductor technologies in terms of losses, electrothermal ruggedness under short circuits, avalanche ruggedness, body diode and conduction performance.

Benchmarking the robustness of Si and SiC MOSFETs: Unclamped inductive switching and short-circuit performance

The reliability and robustness of power devices are key areas of research for increasing the adoption of wide bandgap power semiconductors. This paper benchmarks the robustness under short-circuit (SC) and unclamped inductive switching (UIS) of 650 V SiC trench MOSFETs, SiC planar MOSFETs and silicon super-junction MOSFETs. The performance is characterised at 75 °C and 150 °C and the results show that the SiC MOSFETs have reduced temperature sensitivity under both SC and UIS conditions, which will be beneficial from the application point of view. In the case of the silicon MOSFET, increasing the temperature enhances the short-circuit withstand time as the peak short-circuit current is reduced. The opposite trend is observed for UIS, with a reduction of robustness as the temperature is increased. The absolute SC and avalanche energies are lower for the SiC MOSFETs, but if the chip areas are considered, the energy densities are higher in the SiC MOSFETs, with the SiC Trench having a superior critical SC energy and the SiC planar having a higher avalanche energy density. The higher critical SC and UIS energy densities in SiC MOSFETs, together with their higher thermal resistances result in higher peak junction temperatures and clear hotspots are identified using Finite Element simulations.

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs.

650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance () and lowers the gate-drain capacitance (). It was experimentally shown that a thinner gate oxide further reduces , although with a penalty in terms of increased . A design with 0.5 m half JFET width, enhanced JFET doping concentration of cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.

Crosstalk Induced Shoot-Through in BTI-Stressed Symmetrical & Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, the crosstalk-induced shoot-through current and induced gate voltage of SiC planar MOSFETs, SiC symmetrical double-trench MOSFETs and SiC asymmetrical double-trench MOSFETs is investigated on a half-bridge circuit to analyse the impact of temperature, drain-source voltage switching rate, gate resistance and load current level on crosstalk-induced properties of different SiC MOSFET structures. It shows that due to the smaller gate-source capacitance, the two double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance, which together with the higher transconductance, yield higher shoot-through current than the planar MOSFET. Accordingly, their shoot-through current decreases with increasing of the load current while the planar MOSFET exhibits an opposite trend. The different trend of shoot-through current with temperature on DUTs reveals that the crosstalk in different device structures are dominated by different mechanisms, i.e. threshold voltage and channel mobility with the gate-source capacitance influencing the amplitude. Impact of bias temperature instability with positive and negative gate stressing is measured with a range of stress and recover periods at temperateness ranging between 25 °C to 175 °C. These measurements show that the peak shoot-through correlates with the threshold drift, though with less sensitivity for SiC symmetrical and asymmetrical double-trench MOSFETs compared with the planar SiC MOSFET where the inter-dependence is pronounced. A model is developed for the induced gate voltage and shoot-through current during crosstalk with channel current considered. The comparison of the model results with measurement confirms its capability to predict crosstalk in different MOSFET structures.

Observation of Power MOSFET Composed of Silicon Carbide with a Planar Type in the Voltage Applying State Using a Scanning Probe Microscope

We have developed a scanning probe microscope to evaluate the device with high spatial resolution in a power semiconductor device with a voltage applied. Specifically, we observed the cross sectional structure exposed SiC planar MOS-FET using a multifunctional probe microscope, which combines atomic force microscopy, Kelvin probe force microscopy, and scanning capacitance force microscopy. By observing the channel formation and carrier concentration change in response to the applied voltage, we were able to visualize the internal state of the SiC power MOSFET.

A novel SiC power MOSFET with integrated polySi/SiC heterojunction freewheeling diode

The adoption of intrinsic body diode of SiC MOSFETs as freewheeling diode (FWD) always induces high conduction loss and reverse recovery loss, therefore it is highly desirable to integrate a low loss FWD in SiC MOSFET. In this paper, we propose a new concept of monolithically integrating a polySi/SiC heterojunction diode (HJD) in SiC planar MOSFET (HJDMOS) without sacrificing MOSFET cell density or increasing much processing complexity. The HJD is formed between the gate polysilicon and the SiC JFET region using the same polysilicon deposition, thus the MOSFET and FWD can share the JFET and drift region in a time-multiplexing way. The SiC HJDMOS not only inactivates the body diode by offering lower turn-on voltage but also shows excellent reverse recovery characteristics because the HJD behaves like a Schottky barrier diode. Meanwhile, the gate-to-drain charge (Q gd) and gate-to-drain capacitance (C gd) of the SiC HJDMOS are significantly reduced by 8.0 times and 4.6 times in comparison with the conventional MOSFET due to the reduction of the overlapping area of gate and drain region. With optimal selection of design parameters, the integrated device maintains good MOSFET performances with forward blocking voltage of >1200 V and specific on-resistance (R on,sp) of 2.2 mΩ cm2. Therefore, the obtained figure-of-merits ( and ) of SiC HJDMOS are improved by around 7.5 times and 4.3 times, respectively. The enhanced performances suggest that SiC HJDMOS is an excellent choice for high efficiency and high frequency power electronic applications.

Multiple failure mode identification of SiC planar MOSFETs in short-circuit operation

Due to the high-temperature nature of SiC, SiC MOSFETs can encounter a unique gate failure in SC operation at temperatures below the limit of thermal runaway. This paper aims to identify the two distinct failure modes of SiC planar MOSFETs under specific SC conditions based on the understanding of electro-thermal-mechanical failure physics. The SC failure mode depends on the heating rate and time of two key zones: the source Al adjacent to the upper side of the inter-metal dielectric and the hot spot inside the semiconductor near the JFET region. A 1D multilayer thermal model is used to estimate the transient temperature of the two locations and is validated for a wide range of VDS (from 200 V to 800 V). The model can also predict the failure mode and SCWT using a short turn-on pulse.

Third Quadrant Conduction Loss of 1.2–10 kV SiC MOSFETs: Impact of Gate Bias Control

The third quadrant (3rd-quad) conduction of power MOSFETs involves competing current sharing between the metal-oxide-semiconductor (MOS) channel and the body diode controlled by the gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ). For 1.2 kV SiC planar MOSFETs, it is well known that a positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> higher than the threshold voltage enables parallel conduction through both channels, which reduces the 3rd-quad voltage drop and conduction loss. This work, for the first time, unveils that this fact does not hold for higher voltage (e.g., 3.3 kV and 10 kV) SiC planar MOSFETs. By combining the static characterization, simulation, and modeling, it is revealed that, once the MOS channel turns on, the body diode in high-voltage MOSFETs turns on at a source-to-drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> ) much higher than the built-in potential of the PN junction. In 10 kV SiC MOSFETs, the body diode does not turn on over the entire practical V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> range if the MOS channel is on. As a result, the positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> leads to completely unipolar conduction, which could induce a higher voltage drop than the bipolar body diode at high temperatures. A buck converter based on a 10 kV SiC MOSFET half-bridge module was built and tested, which validated that a negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures. Finally, based on the revealed physics for planar MOSFETs, the optimal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> control for the 3rd-quad conduction in trench MOSFETs is discussed. These results provide critical device understandings of 1.2-10 kV SiC MOSFETs and important application guidelines for 10 kV SiC MOSFETs.

Comparative Study of SiC Planar MOSFETs With Different p-Body Designs

Silicon carbide MOSFET has been commercialized for many years. Its performance is still improving especially for high-frequency application. High-frequency figure-of-merit (HF-FOM) ${R}{ \mathrm{\scriptstyle ON}}^\ast {C}_{\text {GD}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}{}^\ast ~{Q}_{\text {GD}}$ were used for a comprehensive evaluation of the performance of MOSFET. In this article, SiC planar MOSFETs with different p-body designs were comparatively studied. A new planar MOSFET with buffered gate and thick central oxide gate structure (TCOX-MOS) was proposed to further improve the gate oxide electric field in OFF-state and HF-FOM. Compare to the conventional planar MOSFET (C-MOS), the maximum gate oxide electric field, gate–drain charge, and HF-FOM ( ${R}_{ \mathrm{\scriptscriptstyle ON}} {}^{\ast } {Q}_{\text {GD}}$ ) of TCOX-MOS are 32%, 83%, and 84% lower, respectively. Furthermore, TCOX-MOS shows less short-channel effects by better channel shielding structure. The results show that TCOX-MOS is a more attractive device structure.

SiC Planar MOSFETs With Built-In Reverse MOS-Channel Diode for Enhanced Performance

In this paper, the SiC planar MOSFET with built-in reverse MOS-channel diode (SiC MCDMOSFET) is investigated utilizing TCAD simulation tools. When the device is working as a freewheeling diode, the operation of the parasitic body diode is suppressed effectively due to the lower threshold voltage of the MCD. Therefore, the bipolar degradation issue can be completely solved. In addition, the SiC MCD-MOSFET is featuring superior dynamic characteristics. The input capacitance (CISS), reverse transfer capacitance (C RSS ), gate charge (Q G ) and gate-to-drain charge (Q GD ) are reduced by a factor of ~2, ~7, ~2 and ~10, respectively, as compared to the conventional SiC MOSFET (SiC C-MOSFET). Combined with the slightly increased on-resistance (R ON ), tremendously enhanced figures of merit (R ON × Q G and R ON × Q GD are decreased by a factor of 1.8 and 9, respectively) are obtained in the SiC MCD-MOSFET. The outstanding performance and easy-to-implement feature make the SiC MCD-MOSFET more attractive for further power electronic applications.

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Design and Optimization of 1.2-kV SiC Planar Inversion MOSFET Using Split Dummy Gate Concept for High-Frequency Applications

The gate architecture of a 1.2-kV SiC planar MOSFET is engineered to obtain the improved high-frequency figure of merit (HF-FOM) over the split-gate (SG) and planar-gate topology. In this article, we propose a device using the split dummy gate (SDG), which is in short with the source contact at zero potential. The device has a lower reverse transfer/feedback capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rss</sub> or C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) due to the formation of depletion width under SDG and lower gate-to-drain charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) due to reduced overlap with the substrate leading to excellent HF-FOM(R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ). The essential electrical characteristics (such as Ron,sp, breakdown voltage (BV), and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) remain almost similar compared to the device without the dummy gate. The obtained HF-FOM(R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) is 28.7× and 186× lower compared to the device with SG and planar-gate topology, respectively.Using calibrated Sentaurus TCAD simulations, the proposed SDG MOSFET has shown negligible Miller plateau (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ), reduced crowding of the electric field at the SG corner, and improved turn-on/off characteristics with a reduction in switching energies.

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

Increased electrification of traditionally hydraulic and pneumatic functions on aircrafts has put power electronics at the heart of modern aviation. Aircraft electrical power systems have traditionally operated at 115 V AC and 28 V DC with a constant speed generator and transformer rectifier units converting jet engine power into electrical power. However, due to the increasing trend towards the More Electric Aircraft (MEA), 270 V DC systems are likely in the future. This calls into question, the power semiconductor device technology that enables the on-board power converters needed for electro-mechanical actuation as well as solid-state circuit breakers for system protection. Silicon IGBTs have been the work-horse of power electronics, but as switching speeds increase due to the need for high frequency operation, the bipolar nature of IGBT tail currents become a limiting factor for improved energy conversion efficiency. A number of unipolar FET technologies, including SiC trench MOSFETs, SiC planar MOSFETs, silicon super-junction MOSFETs and SiC JFETs in cascode with a low voltage Si MOSFET, have become commercialized at around 650 V. However, reliability and robustness, especially against single event burn-out and/or single event gate rupture is critical. This paper experimentally investigates the performance of the listed FET devices under Unclamped Inductive Switching and Bias Temperature Instability/gate oxide stress tests.

Achieving Reduced Specific On-Resistance in 1.2 kV SiC Power MOSFETs at Elevated Temperature

Power MOSFETs operate at elevated temperatures due to self-heating and hot ambient temperatures. This paper analyzes the increase in on-resistance with temperature for 1.2 kV rated 4H-SiC planar MOSFETs. The impact of various structural parameters are studied using analytical models supported by experimental data. This work defines how to achieve a low ratio [Ron(150°C)/Ron(25°C)] by structural optimization of 1.2 kV SiC planar MOSFETs for the first time. It is found that the inversion mode MOSFETs, fabricated by us in a 6 inch commercial foundry, have a lower ratio [Ron(150°C)/Ron(25°C)] than the accumulation mode MOSFETs, due to a better balance of change in channel and bulk mobility with temperature. Compared with typical commercially available MOSFETs, our fabricated accumulation mode and inversion mode MOSFETs exhibit a lower ratio [Ron(150°C)/Ron(25°C)], resulting in superior HF-FOM [RonxQgd] at 150°C.

Characterization of SiC Trench MOSFETs in a Low-Inductance Power Module Package

This paper evaluates the temperature-dependent static and switching characteristics of SiC Trench mosfet s in a low-inductance multiple-chip power module. First, a phase-leg power module package design with integrated decoupling capacitance is proposed and fabricated based on the P-cell/N-cell concept, and the module design including the substrate layout and packaging material selection are discussed. With the fabricated power module, the temperature-dependent static and switching characteristics of the SiC Trench mosfet s are comprehensively investigated, and the key performance differences from the traditional SiC planar mosfet s are discussed. Specifically, compared to the SiC mosfet s with planar structure, the SiC Trench mosfet s are observed to have a different temperature coefficient in term of the turn- off switching loss. Detailed analysis is provided as well to explain the experimental results.