Abstract
Due to the high-temperature nature of SiC, SiC MOSFETs can encounter a unique gate failure in SC operation at temperatures below the limit of thermal runaway. This paper aims to identify the two distinct failure modes of SiC planar MOSFETs under specific SC conditions based on the understanding of electro-thermal-mechanical failure physics. The SC failure mode depends on the heating rate and time of two key zones: the source Al adjacent to the upper side of the inter-metal dielectric and the hot spot inside the semiconductor near the JFET region. A 1D multilayer thermal model is used to estimate the transient temperature of the two locations and is validated for a wide range of VDS (from 200 V to 800 V). The model can also predict the failure mode and SCWT using a short turn-on pulse.
Published Version
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