Si Removal Research Articles

Metallogenic Model of Bauxite in Central Guizhou Province: an Example of Lindai Deposit

AbstractThe bauxites in central Guizhou are hosted by the Lower Carboniferous Jiujialu Formation. Geochemistrial characteristics of the Lindai bauxite deposit indicate that the underlying Shilengshui Formation dolomite is the precursor rock of mineral resources. Weathering simulation experiments show that Si is most likely to migrate with groundwater, the migration rate of which is several magnitude higher than Al and Fe under nature conditions (pH=3–9). The neutral and acid non‐reducing condition is the most conducive to the Al rich and Si removal, while the acid reducing conditions is the most conducive to the Al rich and Fe removal. In the process of bauxite formation, coal beds overlying the Al‐bearing rock series or other rock formation rich in organic materials can produce acid reducing groundwater, which are important for the bauxite formation. Finally, propose the metallogenic model of the bauxite in central Guizhou Province and put forward three new words which are “original bauxite material”, “bauxite material” and “original bauxite”.

Silicon Substrate Engineered High-Voltage High-Temperature GaN-DHFETs

Low-cost GaN-on-Si-based transistors are targeted to function at high ambient temperatures. With this perspective, it is aimed to evaluate the high-temperature (HT) capabilities of GaN-on-Si double-heterostructure field-effect transistors. It is highlighted that HT device operation degrades both ON and OFF states that are directly related to the increase in the on-resistance and the decrease in device breakdown voltage; 2-DEG mobility drops with increasing temperature and is responsible for ON-state degradation. Regarding the OFF-state operation, it is observed that at low-voltage operation and with increasing temperature, there is an increase in the OFF-state leakage current because of thermal-assisted electrical conduction across the III-N layers and various interfaces. The main breakdown limiting mechanism at any temperature is, however, buffer leakage along the AlN/Si interface. Because this parasitic conduction, a negative temperature coefficient of breakdown voltage of approximately -1 V/°C is observed. For devices after Si removal, the leakage across the AlN/Si interface is interrupted and therefore HT OFF-state characteristics show high potential to be used at high operating voltage. A breakdown voltage as high as ~1800V is observed after Si removal compared with ~500 V with Si at 150°C.

Vapor phase surface preparation (etching) of 4H–SiC substrates using tetrafluorosilane (SiF4) in a hydrogen ambient for SiC epitaxy

Tetrafluorosilane (SiF4) was demonstrated to be a good etchant of SiC substrates. Etch rates of silicon carbide (SiC) substrates using SiF4+H2, SiCl2H2 (DCS)+H2, and C3H8+H2 (at typical SiC growth conditions) were compared to the etch rates found using only H2. While H2 is responsible for C removal, we find that the SiC etch rate is limited by the Si removal rate, leading to liquid Si on the SiC surface. By using propane to prevent Si-droplet formation, the etch rate is significantly reduced to <1µmh−1. SiF4 enhances Si removal from the surface through the formation of SiF2 gas, resulting in an improved liquid Si-free surface with r.m.s. roughness 0.45nm and etch rates as high as 43µmh−1. Weak off-cut dependency was observed for SiF4 etching. At high etch rates (>15µmh−1) the etching becomes more isotropic in the SiC kink and step directions, leading to increased step bunching by the Schwoebel effect. DCS was found to be an ineffective etchant, depositing significant amounts of Si on the surface of SiC (~1–23µmh−1), despite the fact that SiCl2 is a volatile species at this temperature. These differences were explained by comparing Gibbs free energies for various Si-removal pathways.

Improvement of Back-Side Cosmetic Defects And Wafer Strength

The continued challenge to keep up with Moore's law with aggressive device scaling, and shrinking wiring dimensions established perpetual need for novel materials and dictates ever tighter semiconductor process fidelity. Despite large progress with reducing defect densities on the device side of Si wafers, considerably less attention is being paid to the wafer back-side. Back-side wafer defects have been shown to reduce yield by leading to die breakage during packaging processes. Scratches and voids formed on the back-side of the wafer during various manufacturing processes have been shown to create weak spots on the wafer, which can act as initiation points for die crack formation and propagation. In this paper, we present the technical details of a back-side wet etch clean process which helps reducing back-side defect densities significantly. The process is set up on a single wafer wet etch tool at IBM's East Fishkill 300 mm wafer fabrication facility. The process removes the outer back-side layer of the silicon wafer which has become defective and damaged as a result of previous processing steps. This new defect removal process increases die strength, which is measured as wafer mechanical strength, and removes surface defects from the back-side of the wafer. Our results show that removal of 15–30 microns from the wafer back-side reduces the amount of cosmetic defects on the back-side of the wafer by 90%, while increasing die strength by 60%. The effects of the back-side wet etch clean process on the wafer optical appearance and mechanical properties were characterized, and supporting data such as atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), defect inspection, thermal interface material adhesion test, and die strength is included. Results from package level modules indicate an increase in reliability compared to the uncleaned Si back-side. It can be concluded that wet Si removal process described in this paper is a viable method to reduce the back-side defect density with an associated increase in final module product yield.

Interface Oxidative Structural Transitions in Graphene Growth on SiC (0001)

The structural transition from a three-dimensional SiC lattice to a two-dimensional graphene sheet is a crucial element in the growth mechanism of graphene on SiC. An interfacial defective transition layer near the surface of the SiC substrate is believed to be an intermediate structure for graphene layer formation. The transition layer consists of SiOxCy, vacancies, and other defects in the SiC lattice, which result from Si evaporation via thermal degradation of the SiC lattice and oxidation reactions of residual oxygen and other oxygen containing molecules on the SiC surface at high temperatures. This partially oxidized and structurally degraded SiC lattice layer is formed at temperatures lower than the graphene growth temperature but then decomposes with increasing temperature, leading to graphene formation. Then, the growth mechanism for graphene on SiC (0001) in high vacuum consists of multiple steps, including Si removal by thermal decomposition and oxidation, collapsing of the near surface SiC latt...

Modeling and Analysis of Material Removal Characteristics in Silicon Wafer Double Side Polishing

As advancing technologies increase the demand for yield and planarity in integrated circuits, wafers have become larger and their specifications more stringent. Flatness, thickness variation and nanotopography have emerged as important concerns in the wafering process. Double side polishing has been adopted as a solution to these problems. This paper focuses on the material removal characteristics and wafer profile variation during Si double side polishing. A polishing experiment to investigate Si removal characteristics according to process parameters was carried out in a single head rotary polisher equipped with a monitoring system for friction force. It was found that the material removal rate is related to friction energy rate, and the polishing state was transited and divided into three conditions according to pressure. On the basis of the experimental results, the wafer profile variation in double side polishing was modelled and simulated according to pressure. The friction energy was calculated to find the material removal amount across the wafer. With the conversion of calculated friction energy to the material removal amount, wafer profile variation was simulated. As a result, the wafer profile variation and its range were increased with a pressure increase, and originated from the position near the wafer edge.

Characterization of hydrogen–plasma interactions with photoresist, silicon, and silicon nitride surfaces

For the 45 nm technology node and beyond, a major challenge is to achieve reasonably high photoresist ash rates while minimizing the loss of the silicon (Si) substrate and its nitride (Si3N4). Accordingly, an objective of this work is to characterize the photoresist strip rate under varying conditions of H2 plasma and the effects of these conditions on Si and Si3N4 etch rates. In addition, we discuss in detail the fundamental mechanisms of the reactions between H atoms and the above substrates and successfully reconcile the process trends obtained with the reaction mechanisms. In this work, photoresist, Si, and Si3N4 films were exposed to downstream pure-H2 discharges and their removal rates were characterized by ellipsometry as a function of the following parameters: substrate temperature, reactor pressure, H2 flow rate, and source power. The authors found that the H2-based dry ash and Si3N4 etch are both thermally activated reactions, evidenced by the steady increase in etch rate as a function of temperature, with activation energies of ∼5.0 and ∼2.7 kcal/mol, respectively. The Si substrate exhibits a rather unique behavior where the etch rate increases initially to a maximum, which occurs at ∼40 °C, and then decreases upon a further increase in temperature. The decrease in the Si etch rate at higher temperatures is attributed to the activation of competing side reactions that consume the chemisorbed H atoms on the Si surface, which then suppresses the Si-etch step. The photoresist and Si3N4 removal rates increase initially with increasing pressure, reaching maxima at ∼800 and 2000 mTorr, respectively, beyond which the removal rates drop with increasing pressure. The initial increase in removal rate at the low-pressure regime is attributed to the increased atomic-hydrogen density, whereas the decrease in ash rate at the high-pressure regime could be attributed to the recombination of H atoms that could occur by various mechanisms. At temperatures where the reaction rates are relatively fast, the photoresist and Si removal rates both increase continuously with the H2 flow rate, indicating that both reactions are in the supply-limited regime. For the range of process conditions explored here, we find that the etch rates of Si are generally much higher than those for Si3N4 with Si:Si3N4 etch-rate ratios that vary from 25 to ≫520. Based on the process trends obtained here, we have identified a process window—high temperature and intermediate pressure—that attains relatively high photoresist ash rates and low Si and Si3N4 etch rates.

Overcome Challenges in Si/Cu CMP for Back Side TSV

TSV (through silicon via), as an enabling technology for 3D IC manufacturing, has attracted intensive attention in most recent years. It usually includes multiple CMP processes during TSV via formation. For backside TSV, after silicon grinding processes, Si surface may contain heavy defects; backside Si/Cu CMP process ensures a smooth surface finish for next step bonding. Due to its intrinsic nature of the via size and the amount of via filling materials, the technical requirements in TSV CMP are very much different than those in conventional IC CMP technology. The conventional IC Si slurry only cares about Si removal, and conventional Cu slurry only care about Cu removal, neither of this slurry can meet the new requirement for Si/Cu CMP in TSV backside CMP. Apart from that, Si surface in most cases is negative charged, while Cu surface in most cases are positive charged, which may result Cu smearing defect after Si/Cu CMP. These technical differences form the new challenge for CMP users during TSV CMP process in 3D IC manufacturing. In this work, some challenges such as Cu smearing defect in Si/Cu CMP will be discussed in details. It is shown Cu smearing defect can be minimized via slurry formation in backside TSV CMP applications.

First Principles Study of Surface Properties for Silicon Carbide-Derived Structures

Using first-principles ultra-soft pseudo-potential approach of the plane wave based on the density functional theory (DFT), we investigated the surface properties for silicon carbide-derived structure (i.e. SiCDS). The calculated results show that, movement of C and Si atoms caused by Si removal results in surface structural changing, and a nanoporous surface feature can be observed on the SiCDS surfaces when more Si atoms are removed. The mulliken population analysis indicates that the Si removal leads to the stronger chemical bonds between C–Si and the formation of new stronger chemical bands between C–C. From the density of states, as the Si removal proportion increases, C2p becomes gradually dominant in the SiCDS surface state electrons. Moreover, the Si removal leads to evidently different band gaps, indicating that the conductivity for SiCDS surface structures can be adjusted through the Si removal.

Agricultural silica harvest: have humans created a new loop in the global silica cycle?

Silica (Si) is of great concern to agronomists because it has a beneficial effect on plant resistance to various stresses, enabling yield optimization in economically important crop species. Yet biogenic silica (BSi) cycling in soils controls a large part of the Si export fluxes to rivers and oceans. Despite the importance of agricultural‐harvest‐related Si removal, previous studies have not addressed this topic thoroughly. By performing a detailed quantification of agricultural Si export in Western Europe's Scheldt River basin, we show that harvest not only disrupts BSi cycling but also introduces an agricultural Si pathway, with major export Si fluxes as compared with BSi production in climax forest communities and grasslands. Harvesting substantially changes terrestrial Si cycling because reconstitution of BSi to soils in litter fall is prevented. The agricultural Si loop clearly constitutes an important flow of BSi out of terrestrial ecosystems – one that is currently unrecognized in global biogeochemical Si cycling.

Significant enhancement of breakdown voltage for GaN DHFETs by Si substrate removal

AbstractIn this paper, we present a study on the substrate removal of AlGaN/GaN/AlGaN double‐heterostructure FETs (DHFETs) on Si (111) substrates by 2 different approaches: a global versus local removal route. We report on the significant enhancement of breakdown voltage (VBD) of DHFETs with only 2 µm thick AlGaN buffer in both cases. In the case of global Si removal, the Si substrate is completely removed and transferred to the sapphire carrier. However, for the local Si removal, the Si substrate is selectively etched only under the source‐to‐drain regions. Before Si removal, VBD saturates at ∼ 700 V at a gate‐drain distance (LGD) ≥ 8 µm: confirming electrical breakdown into the Si substrate. The breakdown voltage is remarkably enhanced after etching away the substrate by either of the techniques. We measure a VBD &gt; 1100 V for devices with LGD ≥ 15 µm with a buffer thickness of only a 2 µm (© 2011 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

First-principles study of point defects and Si site preference in Al 3Ti

The formation energies of various point defects in Al 3Ti(D0 22) have been calculated by using first-principles calculation. The effects of vacancies on Si site preference were examined to better understand Si substitution behavior in Al 3Ti. The results show that, under Al-rich condition, the formation energy of antisite Al Ti is the lowest than those of other point defects, and Ti vacancy is more preferred than Al vacancy. But Si prefers to occupy Al vacancy compared with Ti vacancy which causes a finite solubility of Si in Al 3Ti system. The calculation is instructive for the further improvements of process of Si removal.

Metal Inserted Poly-Si Stacks with La2O3 Gate Dielectrics for Scaled EOT and VFB Control by Oxygen Incorporation

Metal-Inserted Poly-Si (MIPS) stacks for gate oxide scaling have been presented with La2O3 gate dielectrics. An equivalent oxide thickness (EOT) of 0.69nm can be achieved with good interfacial property by high temperature annealing. The flatband voltage (VFB) can be modulated by oxygen incorporation in conjunction with Si removal process while EOT degradation is less than 1Aå.

Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\mu\hbox{m}$&lt;/tex&gt;&lt;/formula&gt; Buffer Thickness by Local Substrate Removal

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, VBD saturates at ~700 V at a gate-drain distance (LGD) ≥ 8 μm. However, after etching away the substrate locally, we measure a record VBD of 2200 V for the devices with LGD = 20 μm. Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties.

A Novel Si/Cu Slurry for TSV Applications

A novel TSV (Through Silicon Via) Silicon backside polishing slurry has been developed to offer the solution to integration flexibility of TSV applications. The requirements for back-side silicon substrate polishing are to deliver fast silicon removal rate for high throughput, tunable Cu/Si selectivity to achieve desired final topography. Owing to different oxidation properties between silicon substrate and copper metal, it is challenging to achieve both high copper and silicon removal rates with the conventional oxidize, like hydrogen peroxide which also suffers from short slurry pot life. In this study, we investigated a non-peroxide oxidizer, instead of hydrogen peroxide, which can effectively oxidize both silicon and copper metal and to give the relative higher Si and Cu removal rates higher than 0.8μm/min @ 3psi down force, and benefit longer pot life. The Si/Cu selectivity can be fine tuned from 1.6 to 1 as increasing oxidizer concentration from 0.3 to 0.8 wt.%

Novel α-amine-functionalized silica-based dispersions for selectively polishing polysilicon and Si(1 0 0) over silicon dioxide, silicon nitride or copper during chemical mechanical polishing

We modified silica abrasives using the coupling agent n-(trimethoxysilylpropyl)isothiouronium chloride and found that both the polysilicon and Si(1 0 0) removal rates can be enhanced to >1 μm/min when polished using these modified silica-based dispersions at pH 10 and 4 psi down pressure. On adding arginine, lysine or ornithine in these dispersions and maintaining the same pH, both silicon dioxide and silicon nitride removal rates were suppressed to <2 nm/min without affecting the polysilicon and Si(1 0 0) removal rates. All these observed polysilicon, silicon, silicon dioxide and silicon nitride removal rates can be explained based on zeta potential and thermogravimetric data. Interestingly, when abrasive-free solutions which contain only the additives arginine, lysine, guanidine or ornithine were used, polysilicon and Si(1 0 0) removal rates were still >650 nm/min while both silicon dioxide and silicon nitride removal rates were ∼0 nm/min. In addition, removal rate of copper films was <1 nm/min in all the cases.

Silicon Substrate Removal of GaN DHFETs for Enhanced (&lt;1100 V) Breakdown Voltage

In this letter, we present a novel approach to enhance the breakdown voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(V_{\rm BD})$</tex></formula> for AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs), grown by metal–organic chemical vapor deposition on Si (111) substrates through a silicon-substrate-removal and a layer-transfer process. Before removing the Si substrate, both buffer isolation test structures and DHFET devices showed a saturation of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm BD}$</tex></formula> due to the electrical breakdown through the Si substrate. We observed a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm BD}$</tex></formula> saturation of 500 V for isolation gaps larger than 6 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> . After Si removal, we measured a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm BD}$</tex></formula> enhancement of the AlGaN buffer to 1100 V for buffer isolation structures with an isolation gap of 12 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu\hbox{m}$</tex></formula> . The DHFET devices with a gate–drain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> $(L_{\rm GD})$</tex></formula> distance of 15 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> have a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm BD} &gt; \hbox{1100}\ \hbox{V}$</tex></formula> compared with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 300 V for devices with Si substrate. Moreover, from Hall measurements, we conclude that the substrate-removal and layer-transfer processes have no impact on the 2-D electron gas channel properties.

Light extraction enhancement from GaN‐based thin‐film LEDs grown on silicon after substrate removal using HNA solution

AbstractOne of the promising methods to obtain high optical output power from LEDs grown on Si is to eliminate the absorptive Si substrate. In this paper, we report how GaN‐based thin‐film LEDs grown on silicon (111) substrates by MOCVD were successfully transferred to a copper substrate by room‐temperature electroplating and how the original Si substrate was removed by HNA solution. After fabrication, the III‐nitride LED thin films showed no cracks or degradation. And the light output power of LEDs after Si removal increased by ∼ 30% compared with conventional ones before the Si removal. (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

First principles study of surface properties for silicon carbide-derived carbon

The surface properties for silicon carbide-derived carbon (i.e. Si-CDC) are investigated by employing the density functional theory (DFT) plane-wave pseudopotential method. The calculated results show that, the carbon atoms on the Si-CDC first layer, except for the ones linking to sub-layer Si atoms, fall into the second atomic layer, exhibiting a nanoporous surface feature. The Si removal leads to stronger covalent bonding among the C–Si and C–C atoms, implying more stable C atoms on the Si-CDC surface. Different from the case for the SiC, the second atomic layer has the most important contribution on the Si-CDC electrons of surface state. Moreover, the narrower band gap for the Si-CDC surface indicates a superior conductivity.

Study on reaction mechanism of Si and pure CeO2 for chemical-mechanical-grinding process

The thinning process of silicon wafer for power device in automotive applications requires stress relief and relatively high Si removal rate. The innovative process of chemical mechanical grinding (CMG) has been developed for the surface finishing of Si wafer by means of solid state chemical reaction with CeO2 abrasives under dry condition. However, the reaction mechanisms of Si and pure CeO2 in the dry CMG process are yet fully understood. The chips of Si wafer produced during CMG process were analyzed using x-ray diffraction (XRD), transmission electron microscopy (TEM), and TEM/energy dispersive x-ray fluorescence spectrometer. Those analyses clearly indicated that the chips were thin, elongated, and acicular, as well as partially curved. The large amount of Si in amorphous phase and CeO2 were detected in the CMG chips by XRD, except Si crystalline. The reaction experiments between Si and CeO2 were also performed where the pellets composed of mixed Si∕CeO2 powders were heat treated at 400–1200°C in both air and vacuum (10−4torr), then quenched. The specimens heated in air and vacuum above 900°C contained Si, CeO2, a trace of amorphous phase, CeSi1.9 (cerium-silicon alloy), and Ce4.667(Si4)3O (cerium silicate), respectively. This means that the reaction mechanism in heat treatment of the Si∕CeO2 powders is not exactly the same as CMG process. The findings from analyses of CMG chip products proved that the reaction of 2CeO2+Si→Ce2O3+SiO (amorphous) took place during CMG process of Si wafer using CeO2 fixed abrasive. The produced Ce2O3 can be easily transformed to CeO2 by the reaction Ce2O3+1∕2O2→2CeO2.