Si Nanowire Channel Research Articles

Transport Characteristics of Silicon Multi-Quantum-Dot Transistor Analyzed by Means of Experimental Parametrization Based on Single-Hole Tunneling Model.

The transport characteristics of a gate-all-around Si multiple-quantum-dot (QD) transistor were studied by means of experimental parametrization using theoretical models. The device was fabricated by using the e-beam lithographically patterned Si nanowire channel, in which the ultrasmall QDs were self-created along the Si nanowire due to its volumetric undulation. Owing to the large quantum-level spacings of the self-formed ultrasmall QDs, the device clearly exhibited both Coulomb blockade oscillation (CBO) and negative differential conductance (NDC) characteristics at room temperature. Furthermore, it was also observed that both CBO and NDC could evolve along the extended blockade region within wide gate and drain bias voltage ranges. By analyzing the experimental device parameters using the simple theoretical single-hole-tunneling models, the fabricated QD transistor was confirmed as comprising the double-dot system. Consequently, based on the analytical energy-band diagram, we found that the formation of ultrasmall QDs with imbalanced energetic natures (i.e., imbalanced quantum energy states and their imbalanced capacitive-coupling strengths between the two dots) could lead to effective CBO/NDC evolution in wide bias voltage ranges.

TID Effects in Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors Irradiated to Ultrahigh Doses

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions.

Low-noise, high-detectivity, polarization-sensitive, room-temperature infrared photodetectors based on Ge quantum dot-decorated Si-on-insulator nanowire field-effect transistors

A CMOS-compatible infrared (IR; 1200–1700 nm) detector based on Ge quantum dots (QDs) decorated on a single Si-nanowire channel on a silicon-on-insulator (SOI) platform with a superior detectivity at room temperature is presented. The spectral response of a single nanowire device measured in a back-gated field-effect transistor geometry displays a very high value of peak detectivity ∼9.33 × 1011 Jones at ∼1500 nm with a relatively low dark current (∼20 pA), which is attributed to the fully depleted Si nanowire channel on SOI substrates. The noise power spectrum of the devices exhibits a with the exponent, γ showing two different values of 0.9 and 1.8 owing to mobility fluctuations and generation-recombination of carriers, respectively. Ge QD-decorated nanowire devices exhibit a novel polarization anisotropy with a remarkably high photoconductive gain of ∼104. The superior performance of a Ge QDs/Si nanowire phototransistor in IR wavelengths is potentially attractive to integrate electro-optical devices into Si for on-chip optical communications.

Full-band quantum transport simulation in the presence of hole-phonon interactions using a mode-space k·p approach

Fabrication techniques at the nanometer scale offer potential opportunities to access single-dopant features in nanoscale transistors. Here, we report full-band quantum transport simulations with hole-phonon interactions through a device consisting of two gates-all-around in series and a p-type Si nanowire channel with a single dopant within each gated region. For this purpose, we have developed and implemented a mode-space-based full-band quantum transport simulator with phonon scattering using the six-band k · p method. Based on the non-equilibrium Green’s function formalism and self-consistent Born’s approximation, an expression for the hole-phonon interaction self-energy within the mode-space representation is introduced.

Polarity control of carrier injection for nanowire feedback field-effect transistors

We present polarity control of the carrier injection for a feedback field-effect transistor (FBFET) with a selectively thinned p+-i-n+ Si nanowire (SiNW) channel and two separate gates. The SiNW FBFET can be reconfigured in the p- or n-channel operation modes via simple control of electric signals. The two separate gates induce potential barriers in the SiNW channel for selective control of the carrier injection. In contrast to previously reported reconfigurable transistors, our transistor features symmetry of the electrical characteristics for the p- and n-channel operation modes. Positive-feedback operation of the SiNW FBFET provides superior switching characteristics for the p- and n-type configurations, including the on/off ratios (∼ 105) and subthreshold swings (1.36-1.78 mV/dec). This novel transistor is a promising candidate for reconfigurable electronics.

Nondestructive Readout Memory Characteristics of Silicon Nanowire Biristors

In this paper, we demonstrate nondestructive readout memory characteristics of a bistable resistor (biristor) with an ${n}^{+}$ - ${p}$ - ${n}^{+}$ Si nanowire (SiNW) channel on a bendable substrate. The SiNW channel is fabricated using a top–down route, which is compatible with the current complementary metal-oxide-semiconductor technology. The SiNW biristor shows the outstanding memory characteristics such as a retention time of 10 s and a current sensing margin of ~23- $\mu \text{A}$ at room temperature. These memory characteristics originate from a positive feedback process resulting from impact ionization near the p-n junction. Moreover, the positive feedback mechanism is comprehensively investigated using device simulation.

(Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits

Semiconductor nanowire transistors are considered potential successors of finFETs providing the ultimate miniaturization capabilities of MOS transistors and thus targeting ultimate circuit complexity and performance. A promising perspective for further advancement beyond classical CMOS scaling is to exploit functionality enhancement of nanowire transistors. Several nanowire based multi-gated device concepts known as reconfigurable field effect transistors (RFETs) or polarity control FETs that combine multi-functionality with the inherent advantages of silicon nanowires are being currently evaluated [1-4]. These multi-terminal devices merge unipolar n- and p- FET switching characteristics from the same device as selected simply by an electric signal and without the need for doping enabling complementary CMOS operation with a single kind of transistor. RFETs make use of two sharp metal-NiSi2 / intrinsic-silicon interfaces with individual gates for the selective injection of electrons and holes into the channel region [5]. Additional independent steering gates can be integrated to further enhance functionality without comprising on-conductance [6]. In order to allow complementary circuit operation symmetry in the p- and n-type I-Vcharacteristics is mandatory. To this end, we show both experimentally [7] and by device simulations [8] that the application of radial compressive strain to <110> oriented silicon nanowires is able to align the injection efficiency of electrons and holes for diverse nanowire geometries. Full swing complementary operating circuits such as inverters [7] and compact six transistor cells yielding NAND, NOR and minority functions as demonstrated with symmetric RFETs and 3XOR gates with only 8 transistors vs. 24 with CMOS [6,7,10,11]. These gates build the basis for arithmetic building blocks such as one-bit adders with substantially lower transistor count reducing critical pathes, delay and power consumption as compared to conventional CMOS [6]. The RFET concept has been recently successfully transferred to a parallel nanowire technology [12,13] principally enabling to build low operation power circuits and sensors on plastic substrates. Finally, we show that germanium based RFETs improve the individual device performance and to reduce dynamic power consumption without comprising static power consumption. Figure caption: a) Schematic of reconfigurable nanowire FET (RFET) encompassing intrinsic Si nanowire channel and two independently gated Si / NiSi2 junctions. b) Oxide induced compressive stress in Si nanowire core required to adjust electron and hole currents: TEM cross section of nanowire channel with overlay of computed mechanical strain distribution. c) SEM image of abrupt Si / NiSi2 junction. d) SEM of symmetrically operating RFET with electrical device symbol. e) Symmetric p- and n-program I-V transfer characteristics of device depicted in d). f) SEM of inverter built of two RFETs within a single nanowire. g) Measured inverter transfer characteristic with supply voltage of Vdd = 2V showing low operation power complementary behavior and full swing output. Propagation delay for scaled structure and for different fanouts. Output of reconfigrable NAND/NOR/Minority 6-transistor cell, shows reconfiguration at runtime (mixed -mode computations). h) High-yield printed silicon nanowire FETs encompassing ~ 1xE3 parallel nanowires with meander source/ drain / gate structure. Technology is compatible with flexible plastic substrates.

In‐Plane Self‐Turning and Twin Dynamics Renders Large Stretchability to Mono‐Like Zigzag Silicon Nanowire Springs

Crystalline Si nanowire (SiNW) springs, produced via a low temperature (&lt;350 °C) thin film technology, are ideal building blocks for stretchable electronics. Herein, a novel cyclic crystallographic‐index‐lowering self‐turning and twin dynamics is reported, during a tin‐catalyzed in‐plane growth of SiNWs, which results in a periodic zigzag SiNW without any external parametric intervention. More interestingly, a unique twin‐reflected interlaced crystal‐domain structure has been identified for the first time, while in situ and real‐time scanning electron microscopy observations reveal a new twin‐triggering growth mechanism that is the key to reset a complete zigzag growth cycle. Direct “stress–strain” testing of the SiNW springs demonstrates a large stretchability of 12% under tensile loading, indicating a whole new strategy and capability to engineer mono‐like SiNW channels for high performance stretchable electronics.

Fabrication and characterisation of suspended narrow silicon nanowire channels for low-power nano-electro-mechanical (NEM) switch applications

Suspended silicon nanowires with narrow (∼10nm) conduction channel are fabricated and characterised for further development of low power nano-electro-mechanical (NEM) switching devices using CMOS compatible fabrication. Double suspension fabrication process using an amorphous silicon sacrificial layer and xenon difluoride etching is employed for thermally-oxidised suspended Si nanowire channels. Device current–voltage characteristics demonstrate depletion mode operation of heavy doped nanowires with an on/off ratio of 105 and a threshold voltage of −1.8V. In plane electromechanical pull-in to side gate is demonstrated and confirmed to be consistent with finite element analysis.

Use of Field-Effect Density Modulation to Increase ZT for Si Nanowires: A Simulation Study

Modulation doping is a promising means of increasing the electrical conductivity of thermoelectric (TE) materials and achieving a high figure of merit (ZT). We compared, qualitatively and quantitatively, the TE performance of a field-effect density modulated Si nanowire channel of diameter D = 12 nm with that of its doped counterpart, by use of self-consistent atomistic tight-binding simulations coupled to the Boltzmann transport equation. We describe the simulation model, and show that as a result of a large improvement in electrical conductivity, gating, rather than doping, can result in greater than three-fold improvement of the TE power factor. Despite the large increase in the electronic part of the thermal conductivity, the total thermal conductivity is still dominated by phonons. Thus, a ZT more than three-fold higher can also be achieved in the gated channel compared with the doped channel. Finally, we show that the power factor peak is obtained when the Fermi level resides ∼k B T below the band edge, as is observed for doped channels.

Non-volatile memory effect of a high-density NiSi nano-dots floating gate memory using single triangular-shaped Si nanowire channel

A back-gated nonplanar floating gate device based on buried single triangular-shaped Si nanowire channel (width ∼40 nm) and embedded high-density uniform NiSi nano-dots (∼1.5×1012 cm−2) is demonstrated. Memory properties including memory window, programming/erasing, and retention are evaluated. The transfer and transient characteristics show clear charge injection, storage and removal effects and the associated programming/erasing mechanism based on fringing electric field is studied. Robust room and high temperature retention performance is observed.

Realization of Al tri-gate single electron turnstile co-integrated with a close proximity electrometer SET

This paper presents a novel fabrication process to realize high density silicon based quantum dot devices with close proximity Al and Si gates on ultrathin silicon-on-insulator for spin qubit applications. Al gates surrounding a Si nanowire channel can adjust tunnelling barrier height electrically, while Si plunger side gates enable precise control of the quantum dots potential. This device is fabricated using a multi-layer electron beam lithography process that is fully compatible with metal oxide semiconductor technology. Low temperature electrical measurements and Coulomb oscillation characteristics have demonstrated the capability of this structure to electrostatically define two coupled single electron transistors, one to be used as a turnstile device and the other as an electrometer.

Evaluation of a Gate Capacitance in the Sub-aF Range for a Chemical Field-Effect Transistor With a Si Nanowire Channel

An evaluation of the gate capacitance of a field-effect transitor (FET), whose channel length and width are several ten nanometer, is a key point for sensors applications. However, experimental and precise evaluation of capacitance in the attofarad range or less has been extremely difficult. Here, we report an extraction of the capacitance down to 0.55 aF for a Si FET with a nanoscale wire channel, whose width and length are 15 and 50 nm, respectively. The extraction can be achieved by using a combination of four kinds of measurements: current characteristics modulated by double gates, random-telegraph-signal noise induced by trapping and detrapping of a single electron, dielectric polarization noise, and current characteristics showing Coulomb blockade at low temperature. The extraction of such a small gate capacitance enables us to evaluate electron mobility in a nanoscale wire by using a classical model of current characteristics of an FET.

Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7×12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing ~99 mV/dec, and high ION/IOFF >; 107 (VD = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

Application of ALD High-k Dielectric Films as Charge Storage Layer and Blocking Oxide in Nonvolatile Memories

ALD high-k dielectric films of HfO2 were utilized for the charge trapping layer and Al2O3 for the blocking oxide layer during fabrication of several Metal/Al2O3/HfO2/SiO2/Si (MAHOS) non-volatile memory (NVM) cells based on Si nanowire channel. Si nanowires grown from predefined Au catalysts were integrated into memory devices by using a self-aligning approach. For benchmarking and comparison a different Metal/SiO2/HfO2 /SiO2/Si (MOHOS) nonvolatile memory cell with a SiO2 blocking layer was also processed. All the Si nanowire nonvolatile memory cells show a large memory window, good endurance and retention, however, the MAHOS cells with Al2O3 blocking layers outperform the MOHOS cell with SiO2 blocking layer.

Strong dependence of tunneling transport properties on overdriving voltage for room-temperature-operating single electron/hole transistors formed with ultranarrow [100] silicon nanowire channel

The single electron/hole transistor (SET/SHT) consisting of a Si nanowire channel with a self-assembled Si quantum dot showed a strong dependence of Coulomb blockade (CB) characteristics on the overdriving voltage (Vover). The SET/SHT requiring a low Vover due to the moderate dot size compared to the nanowire size showed good device performances, for example, very sharp CB oscillation and long extension of blockade regime. However, the SET/SHT requiring a high Vover due to the unduly shrunken of size, which leads to an increase in the valence band offset between the dot and the nanowire, showed the drastic degradation of the device performances.

Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor

A unique feature of the extremely long-range-extended blockade regime with its shape of a long stick, where the Coulomb blockade oscillation and negative differential conductance peak-positions can be systematically and precisely modulated for both extremely-wide VG and VD ranges, was clearly observed in a room-temperature-operating silicon single hole transistor. These results originate from the large quantum level spacing, large tunnel-barrier height, small tunnel-barrier curvature, small bias-induced barrier modulation, and large voltage gain, attributing to the formation of an ultrasmall dot in the gently sloped tunnel barriers along the [100] Si nanowire channel having the large subband modulation.

Simulation of a triple-gate single electron FET memory with a quantum dot floating gate and a quantum wire channel

This paper investigates a triple-gate single electron FET memory with a Si quantum dot floating gate and a Si quantum wire channel by establishing a numerical model of two-dimensional Schrdinger and Poisson equations. The electron concentration in the silicon quantum wire channel of different scales is investigated under conditions that diverse gate voltage and programming voltage are applied with a two-dimensional finite element solution. The influence of the quantum confinement effect and the electron distribution in the nano-scale channel on the structure is also investigated. Results of the simulation show that, the threshold voltage increases when the size of the channel decreases, and the voltage also increases as the number of electrons on the floating gate increases. However, a non-linear saturation tendency occurs when the number of injected electrons increases further, due to the high density of carriers in the nanoscale Si nanowire channel. Further research shows that the strong quantum confinement effect in the channel can effectively restrain the saturation tendency when the size of the channel is small enough. It's worth mentioning that the threshold voltage shift reflects the number of electrons stored on the floating gate.This effect implies a possibility of multi-level storage.

Atomistic Modeling of Gate-All-Around Si-Nanowire Field-Effect Transistors

We report atomistic simulations of the transport properties of Si-nanowire (SiNW) field-effect transistors. Results have been obtained within a self-consistent approach based on the nonequilibrium Green's function (NEGF) scheme in the density functional theory framework. We analyze in detail the operation of an ultrascaled SiNW channel device and study the characteristics and transfer characteristics behavior of the device while varying several parameters including doping, gate and oxide lengths, and temperature. We focus our attention to the quantum capacitance of the SiNW and show that a well-tempered device design can be accomplished in this regime by choosing suitable doping profiles and gate contact parameters.

High-performance TFTs with Si nanowire channels enhanced by metal-induced lateral crystallization

Thin-film transistors with poly-Si nanowire (NW) channels enhanced by metal-induced lateral crystallization (MILC) are reported. The new device features a side-gate with self-aligned NW channels abutting the sidewalls of the gate structure. By adopting the MILC technique, the crystallinity of the NW channels is greatly enhanced, compared to those formed by solid-phase crystallization. As a result, the electrical performance of the devices could be significantly enhanced in terms of reduced subthreshold swing and threshold voltage as well as improved field-effect mobility.