Si Nanowire Channel Research Articles

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA/μm were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Silicon Vertically Integrated Nanowire Field Effect Transistors

Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.