Si Nanosheet Research Articles

Low Temperature Selective Epitaxy of Group-IV Semiconductors for Nanoelectronics

We have evaluated low temperature epitaxy (LTE) of Phosphorous doped Si (Si:P) and Boron doped SiGe (SiGe:B) on Si(001) substrates. The benefit of LTE is very significant, enabling incorporation of high levels of active dopant for both p- and n-type layers. This translates into lower resistivity compared to layers grown at higher temperature. However, several challenges appear when epitaxy occurs at low temperature (e.g., <500ºC): (i) low growth rate; (ii) loss of selectivity and (iii) crystallinity degradation, particularly on non-(001) surfaces. To overcome these issues, careful selection of precursors and optimization of process conditions is required. In this work, we discuss layer properties obtained on blanket Si(001) wafers. We have also evaluated the most promising SiGe:B growth conditions on patterned nanosheet structures, where the layer was shown to be selective towards SiN and SiO2 and crystalline growth was realized on Si(110) nanosheet sidewalls. Finally, selective process layer uniformity and wafer-to-wafer reproducibility were assessed over twenty Si(001) wafers showing excellent layer uniformity and wafer-to-wafer repeatability.

Transfer learning approach to analyzing the work function fluctuation of gate-all-around silicon nanofin field-effect transistors

With the shrinking of technological nodes, analysis of nanosized-metal-grain pattern-dependent devices is becoming critical; various machine learning (ML) approaches have been utilized to study device characteristic and variability. The inevitable dataset, one of the requisite ML techniques, can be overcome by considering the transfer learning (TL) approach. In this work, an analysis of electrical characteristic affected by work function fluctuation (WKF) with a limited amount of dataset of gate-all-around (GAA) silicon (Si) nanofin (NF) field-effect transistors (FETs) is advanced along with the combination of collected data of GAA Si nanosheet (NS) FETs and TL models. Comparison of the baseline ML model and the proposed TL model shows significant improvement in terms of the values of root mean square error (RMSE) and R2-score. One of applications of this work is to estimate the WKF-induced variability without executing a huge amount of three-dimensional device simulation of GAA Si NF FETs.

Tunneling leakage in ultrashort-channel MOSFETs—From atomistics to continuum modeling

The channel lengths of transistors are now nearing the nanometer, making these devices increasingly prone to direct source-to-drain tunneling (DSDT), a leakage mechanism commonly considered to set the end of Moore’s law. In MOSFETs, the probability for a charge carrier to undergo DSDT decays exponentially with channel length, source depletion length, and drain depletion length. Bound-charge engineering (BCE) is a recently introduced scheme where the depletion lengths of FETs can be controlled through effective doping by surface bound charges residing on the interface between a semiconductor and an adjacent oxide. In this letter, BCE is applied to reduce DSDT leakage current down to acceptable levels in MOSFETs with channels as short as 2.3nm; the higher the oxide permittivity, the lower the DSDT leakage. This idea is tested on ultrascaled Si nanowire MOSFETs via atomistic quantum transport simulations based on the nonequilibrium Green’s function (NEGF) formalism and the tight-binding model, as well as on physically larger Si nanosheet MOSFETs via continuum NEGF–k·p simulations based on the finite-element method.

Efficient and stable activation by microwave annealing of nanosheet silicon doped with phosphorus above its solubility limit

The relentless scaling of semiconductor devices pushes the doping level far above the equilibrium solubility, yet the doped material must be sufficiently stable for subsequent device fabrication and operation. For example, in epitaxial silicon doped above the solubility of phosphorus, most phosphorus dopants are compensated by vacancies, and some of the phosphorus-vacancy clusters can become mobile around 700 °C to further cluster with isolated phosphorus ions. For efficient and stable doping, we use microwave annealing to selectively activate metastable phosphorus-vacancy clusters by interacting with their dipole moments, while keeping lattice heating below 700 °C. In a 30-nm-thick Si nanosheet doped with 3 × 1021 cm−3 phosphorus, a microwave power of 12 kW at 2.45 GHz for 6 min resulted in a free-electron concentration of 4 × 1020 cm−3 and a junction more abrupt than 4 decades/nm. The doping profile is stable with less than 4% variation upon thermal annealing around 700 °C for 5 min. Thus, microwave annealing can result in not only efficient activation and abrupt profile in epitaxial silicon but also thermal stability. In comparison, conventional rapid thermal annealing can generate a junction as abrupt as microwave annealing but 25% higher sheet resistance and six times higher instability at 700 °C.

Bifunctional catalysts composed of low silicon‐content SAPO‐34 nanosheets and In2O3/ZrO2 with improved performance for CO2 hydrogenation

AbstractThe conversion of CO2 into high‐value chemicals has drawn a great deal of consideration, of which the most ideal product is lower olefins. However, the modified Fischer–Tropsch (F‐T) synthesis with CO as an intermediate shows poor selectivity for lower olefins. Here, a list of bifunctional catalysts consisting of SAPO‐34 zeolites with adjustable silicon contents and In2O3/ZrO2 were synthesized. In the reaction process, CO2 is first hydrogenated to methanol over an In2O3/ZrO2 catalyst, and then the generated methanol rapidly diffuses to the adjacent zeolite catalyst to react to lower olefins. The selectivity of lower olefins (88.3%) and conversion rate of CO2 (23.3%) was achieved over In2O3/ZrO2 and SAPO‐34‐0.05 at 633 K, a gas hourly space velocity (GHSV) of 4500 ml·gcat–1·h–1, and H2/CO2/Ar = 3:1:1. The catalytic performance remained stable after 50 h of reaction. Characterization analysis showed that Si content affected the content of Brønsted acid sites (BAS) and morphology of SAPO‐34, resulting in different distribution of reaction intermediates. Tetramethyl‐benzenes, as important intermediate species, had a slower conversion rate on the SAPO‐34 with low Si content and nanosheet morphology, which led to high lower olefins selectivity. © 2022 Society of Chemical Industry and John Wiley &amp; Sons, Ltd.

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

In this paper, in order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer (SIT) and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanscale fins at the same time, which increase the volumes of electrical conductance pathway between NS channels and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those of w./o. LPs. Therefore, ∼3 times and ∼2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ </tex-math></inline-formula> ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

P-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. The Si NS MOSFETs provide high current drivability due to wider effective channel (W eff) and maintain better short channel performance. Here, the performance of junctionless (JL) SOI NS p-MOSFET is evaluated by invoking HfxTi1−xO2 gate stack to overcome adverse short channel effects (SCEs). The device performance is enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on I ON/I OFF, SS, V th is presented and the analog/RF metrics of the device are evaluated. The power consumption, dynamic power, and static power analyses of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an I ON/I OFF ratio of more than ∼106 with NS widths of 10 to 30 nm, respectively. The device exhibits better performance (I ON) with higher NS widths and ensures potential towards high-performance applications. However, with an increase in NS widths the threshold voltage (V th) tends to downfall and leads to deterioration in subthreshold performance . With high-k spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

RF Performance of Stacked Si Nanosheet nFETs

Stacked nanosheet nFETs considering a six-stack four-finger transistor array are studied and optimized by validated TCAD simulation. Stacked Si nanosheet (NS) nFETs have lower parasitics than nFinFETs in the same six-fin/stack four-finger transistor array layout. With the same electron mobility, back-end-of-line (BEOL), equivalent oxide thickness (EOT) of 1.4 nm, and gate length of 30 nm, the stacked Si NSs have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1\times $ </tex-math></inline-formula> cut-off frequency (240 versus 215 GHz) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.15\times $ </tex-math></inline-formula> maximum oscillation frequency (290 versus 251 GHz) when compared to FinFETs due to larger transconductance increase than capacitance increase and output conductance decrease. With the optimized EOT of 0.8 nm and gate length of 18 nm, the stacked Si NSs can achieve cut-off frequency of 340 GHz and maximum oscillation frequency of 370 GHz. Furthermore, considering the higher electron mobility on {100} surfaces of NSs than {110} sidewalls of FinFETs as suggested by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{D}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}}$ </tex-math></inline-formula> fitting, the cut-off frequency and maximum oscillation frequency of stacked Si NSs can reach 380 and 390 GHz, respectively.

Ultrathin Multibridge Channel Transistor Enabled by van der Waals Assembly.

Multibridge channel field-effect transistors (MBCFETs) enable improved gate control and flow of a large drive current and they are regarded as promising candidates for next-generation transistor architecture. However, in achieving a larger drive current with a thinner channel, limitations arise from the decrease in mobility when the thickness of the Si nanosheet is less than 5nm. In addition, an increase in the leakage current is unavoidable when a large number of channels are stacked. Here, a 2D ultrathin MBCFET is demonstrate, constructed based on 2nm/2nm MoS2 channels. The normalized drive current (23.11 µA*µmµm-1 ) in each level channel of this MBCFET exceeds that of the latest seven-level-stacked Si MBCFET, while the leakage current is only 0.4% of this value, with the subthreshold swing reaching 60mVdec-1 and an on/off ratio reaching up to 4×108 at room temperature. Furthermore, the drive current of this 2D ultrathin MBCFET can be further increased by regulating the polarity of the operation voltage to reduce the injection barrier. The combination of 2D materials and an MBC structure has the potential for use in high-performance and low-power-consumption electronics.

Characteristics of Stacked Gate-All-Around Si Nanosheet MOSFETs With Metal Sidewall Source/Drain and Their Impacts on CMOS Circuit Properties

In this brief, we computationally examine electrical characteristics of stacked gate-all-around Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) source/drain (S/D) by increasing the number of channels (NCs) and their impacts on digital circuits. The ON-current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) and circuit performances of the NS-FETs without the MSW S/D are limited to three channels due to the electrostatic potential decreasing from the top contacts to the bottom S/D side of NS-FETs; however, the MSW S/D can improve the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> with increasing the NCs over three channels because of low resistivity of tungsten ( 5.6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> Ω·cm) in the sidewall of S/D and then the circuit performances can be boost by the MSW S/D structure of the stacked GAA NS-FETs over three channels. For example, up to six channels of the NS-FETs with the MSW S/D, the frequency of ring oscillator is 57% increase, compared with the case without MSW S/D. The results of this study can be considered to design the S/D structure of the stacked GAA NS-FETs in emerging device technologies.

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

Fine structural and photoluminescence properties of Mg2Si nanosheet bundles rooted on Si substrates

Creating vertically aligned 2D nanostructures is a promising approach to achieving advanced electronic and optoelectronic materials. In this study, Mg2Si nanosheet bundles were synthesized by Ca atom extraction from CaSi2 microwalls grown on Si substrates via thermal annealing in a MgCl2/Mg mixed vapor. The nanosheet bundle structure was modified to compound nanosheet bundles from previously reported Si nanosheet bundles. The observed Mg2Si nanosheets consist of thin Mg2Si layers, and well-defined fine-scale Mg2Si superlattice-like structures were achieved in the nanosheet bundles. In addition, the Raman scattering and photoluminescence properties were examined, and structural and electronic modifications of the nanosheet bundle compared with the bulk crystals were suggested. To obtain tailored properties and functionalities of the nanosheet bundles, structural modification of layered crystals is a useful technique.

Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors

Gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are the most promising candidates to replace FinFETs and nanowire (NW) FETs in future technology nodes owing to their improved short-channeleffects, high current drivability per layout footprint (LF), and extreme scalability. The much-needed voltage scaling in these aggressively scaled devices can be provided by introducing negative capacitance (NC) effect, which results in sub-60 mV/decade switching behavior. In this article, we explore how NC effect manifests into silicon NS transistors by using technology computer aided designs (TCAD). The NC effect originates from a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) configuration in the gate-stack. The performance of single channel NC-NSFET is benchmarked against NC-NWFET and NC-FinFET of comparable device dimensions. NC-NSFET shows 9% and 38% lower subthreshold swing when compared to NC-NWFET and NC-FinFET, respectively. For NC-NSFETs, capacitance matching, between the ferroelectric (FE) and the underlying MOS capacitance, is achieved with a thinner FE layer. Between single stack and double stack devices, single stack NC-NSFET offers faster switching at low operating voltages. Within a stack, nonuniformity in NS cross sections is found to influence device behavior. We also report the performance of NC-NSFETs in terms of key device design parameters, like channel length, thickness, and width of NS, and metal work function (WF), where, thinner NSs and metals with high WF provide significant enhancement in I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio. The results presented here can aid in the design, operation, and performance improvement of emerging NC-NSFET devices.

Electronic and vibrational properties of pristine and Cd, Si, Zn and Ge-doped InN nanosheet: a first principle study

Within density functional theory, structural, electronic and vibrational properties of pure and Cd, Si, Zn and Ge-doped InN nanosheet have been investigated using B3LYP/LanL2DZ method. The structural stability is described by using calculated energy and vibrational study. The HOMO–LUMO gap, ionisation potential (IP), electron affinity (EA) and hardness of the optimized nanosheet are discussed. The present study implying that the variation in the energy gap due to the impurity substitution could be attributed to sensitivity of InN nanosheet towards a specific dopant signifies that we can tune the electronic properties by applying particular impurity. The study of vibrational frequency ensures that the structures are located at minimum position on potential energy surface (PES). The IR and Raman activity spectrum are evaluated. High value of IP and EA infers pleasant condition for chemical sensors.

Effects of Nanotopography Regulation and Silicon Doping on Angiogenic and Osteogenic Activities of Hydroxyapatite Coating on Titanium Implant.

BackgroundAngiogenic and osteogenic activities are two major problems with biomedical titanium (Ti) and other orthopedic implants used to repair large bone defects.PurposeThe aim of this study is to prepare hydroxyapatite (HA) coatings on the surface of Ti by using electrochemical deposition (ED), and to evaluate the effects of nanotopography and silicon (Si) doping on the angiogenic and osteogenic activities of the coating in vitro.Materials and MethodsHA coating and Si-doped HA (HS) coatings with varying nanotopographies were fabricated using two ED modes, ie, the pulsive current (PC) and cyclic voltammetry (CV) methods. The coatings were characterized through scanning electron microscope (SEM), X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FT-IR), X-ray photoelectron spectrometer (XPS), and atomic force microscopy (AFM), and their in vitro bioactivity and protein adsorption were assessed. Using MC3T3-E1 pre-osteoblasts and HUVECs as cell models, the osteogenic and angiogenic capabilities of the coatings were evaluated through in vitro cellular experiments.ResultsBy controlling Si content in ~0.8 wt.%, the coatings resulting from the PC mode (HA-PC and HS-PC) and CV mode (HA-CV and HS-CV) had nanosheet and nanorod topographies, respectively. At lower crystallinity, higher ionic dissolution, smaller contact angle, higher surface roughness, and more negative zeta potential, the HS and PC samples exhibited quicker apatite deposition and higher BSA adsorption capacity. The in vitro cell study showed that Si doping was more favorable for enhancing the viability of the MC3T3-E1 cells, but nanosheet coating increased the area for cell spreading. Of the four coatings, HS-PC with Si doping and nanosheet topography exhibited the best effect in terms of up-regulating the expressions of the osteogenic genes (ALP, Col-I, OSX, OPN and OCN) in the MC3T3-E1 cells. Moreover, all leach liquors of the surface-coated Ti disks promoted the growth of the HUVECs, and the HS samples played a more significant role in promoting cell migration and tube formation than the HA samples. Of the four leach liquors, only the two HS samples up-regulated NO content and expressions of the angiogenesis-related genes (VEGF, bFGF and eNOS) in the HUVECs, and the HS-PC yielded a better effect.ConclusionThe results show that Si doping while regulating the topography of the coating can help enhance the bone regeneration and vascularization of HA-coated Ti implants.

Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs

The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The Vt difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher Vt difference due to the higher thermal resistance and stronger temperature dependence of Vt than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The Vt difference increases with the increasing channel number and nanosheet width.

(Invited) Low-Energy Plasma Enhanced Chemical Vapor Deposition and In-Situ Doping for Junction Formation in Group-IV Semiconductor Devices

In novel semiconductor devices, such as a tunnel field-effect transistor (TFET) [1,2], a resonant-tunneling device [3-5] and a semiconductor spin qubit [6], energy-band modulation in group -IV semiconductors using nanometer-scale heterostructure and local doping [7] with suppressed intermixing is a key technology. Additionally, 2-dimensional (2D) nanosheet semiconductor materials (e.g. graphene, silicene, tungsten disulfide and so on) are aggressively investigated [8]. In such a trend, as well as conventional low-temperature thermal processes, utilizing a low-energy plasma process has been explored. We have clarified that low-energy Ar plasma irradiation effectively induces surface reaction and epitaxy of Si-based group-IV semiconductor on Si(100) [9-19]. Our efforts in development of such material processing utilizing low-energy Ar plasma process will be presented. Without substrate heating, low-energy electron-cyclotron-resonance (ECR) Ar plasma chemical-vapor deposition (CVD) process has enabled epitaxy of strained/unstrained films of group-IV materials (Si, Ge, Si-Ge alloy and Si-C alloy) with in-situ doping and an atomic-layer (AL) doped structure (Fig. 1) [9-19]. Especially in the TFET, sub-nanometer-order (atomic-order) abrupt profile control of impurities (B or P) concentration will be examined in epitaxy and in-situ doping. As a typical issue in our plasma CVD, it is considered that surface segregation of impurity during Si deposition occurs and degrades the profile abruptness near the interface. However, it has been demonstrated that the abruptness can be improved by atomic-layer doping technique [14,18]. Additionally, it is found that electrical activity of B doped in Si tends to be lowered especially at higher concentration than 1019 cm-3, while higher-energy plasma irradiation effectively improves the activity. These imply that semiconductor device process can be performed at lower temperatures where unexpected thermal diffusion and reactions are effectively suppressed. Our recent challenge is penta-silicene formation from epitaxial Si nanosheet. We believe that 2D materials as a novel semiconductor will be obtained not only by atomically-controlled epitaxy of heterostructures but also by reconstruction of atomic arrangement at surface. Here, our target is penta-silicene transformed from a 3-atomic-layer-thick Si nanosheet, which is different from the diamond structure. Our concept is crystal structure transformation in the Si nanosheet, and this is based on long-range coordinated and double-sided surface reconstruction on Si(100) to form the penta-silicene (Fig. 2) [15]. Because penta-silicene has a 3-dimensional structure composed of 3 atomic layers (similar to tungsten disulfide), it is expected to be more stiff and stable physically than monolayer of hexa-silicene. Realization methods of the penta-silicene on Si wafer for large-scale integration of the penta-silicene devices are now in progress. After formation of penta-silicene, control of interface structure between the penta-silicene and gate insulator will be one of the important issues to control interface structure. From the view-point of material science and control of the interfaces in semiconductor, development of process technology must be proceeded further. Such efforts will encourage smart electronic devices for enabling artificial intelligence and higher security in the next-generation information society. Acknowledgements This work was partly supported by Grant-in-Aid for Challenging Exploratory Research (No. 18K18987) from the JSPS in Japan and the Cooperative Research Project Program of the Research Institute of Electrical Communication, Tohoku University.

Synthesis, structural and photoluminescence properties of Mg2Si/Si nanocomposites consisting of Si nanosheet bundles and Mg2Si deposits

Mg2Si/Si nanocomposites, consisting of Si nanosheet bundles and Mg2Si deposits formed on the Si nanosheet bundles, were formed by the thermal annealing of CaSi2 powders in MgCl2 vapor. Mg atoms are deposited on the Si nanosheet bundles, and the surface of the nanosheets were partially transformed into the Mg2Si phase during the thermal treatment. The Mg2Si/Si composites were also synthesized on Si(111) substrates. The structural and photoluminescence (PL) properties of the composites were characterized. The Mg2Si deposits were inhomogeneously distributed on the Si nanosheets. Furthermore, the Si-based nanosheets consisted of disordered thinner Si layers, and a disordered superlattice-like layered structural model is shown. The PL emissions in the visible region were clearly observed, and the temperature and the excitation intensity dependences of the emissions were characterized. It was found that the structural modification of the Si nanosheet bundles to form the composites with Mg2Si deposits affected the emission property of the Si nanosheets. The luminescence mechanism of the composite was discussed.

Aluminum and phosphorene based ultrasensitive SPR biosensor

In order to designing an ultrasensitive biosensor with high detection accuracy, a bimetallic (Al/Au) structure is proposed. Further sensitivity enhancement is obtained by applying Si nanosheet and some 2D materials. Few-layer phosphorene, graphene and tungsten disulfide are selected to enhance the angular sensitivity of the biosensor. Different coupling prisms are examined due to obtaining the best response. Considering the achievable highest sensitivity together with smallest minimum reflectance values, the optimized number of layers for each material is selected. Finally, 258% sensitivity enhancement with 3 nm Au, 7 nm Si and 5 layers of phosphorene on Al surface is obtained compared with bare Al-based SPR biosensor.