Abstract
The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The Vt difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher Vt difference due to the higher thermal resistance and stronger temperature dependence of Vt than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The Vt difference increases with the increasing channel number and nanosheet width.
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