Si Nanowire MOSFETs Research Articles

Triple-metal gate work function engineering to improve the performance of junctionless cylindrical gate-all-around Si nanowire MOSFETs for the upcoming sub-3-nm technology node

Triple-metal gate work function engineering to improve the performance of junctionless cylindrical gate-all-around Si nanowire MOSFETs for the upcoming sub-3-nm technology node

Tunneling leakage in ultrashort-channel MOSFETs—From atomistics to continuum modeling

The channel lengths of transistors are now nearing the nanometer, making these devices increasingly prone to direct source-to-drain tunneling (DSDT), a leakage mechanism commonly considered to set the end of Moore’s law. In MOSFETs, the probability for a charge carrier to undergo DSDT decays exponentially with channel length, source depletion length, and drain depletion length. Bound-charge engineering (BCE) is a recently introduced scheme where the depletion lengths of FETs can be controlled through effective doping by surface bound charges residing on the interface between a semiconductor and an adjacent oxide. In this letter, BCE is applied to reduce DSDT leakage current down to acceptable levels in MOSFETs with channels as short as 2.3nm; the higher the oxide permittivity, the lower the DSDT leakage. This idea is tested on ultrascaled Si nanowire MOSFETs via atomistic quantum transport simulations based on the nonequilibrium Green’s function (NEGF) formalism and the tight-binding model, as well as on physically larger Si nanosheet MOSFETs via continuum NEGF–k·p simulations based on the finite-element method.

The Short Channel and Quantum Confinement Effects on Transfer Characteristics of Si NWMOSFET Depending on the Gate Length and Temperature

With advancements in nanomaterial synthesis, semiconductor device technology entered a new era with nanotechnology. In fact, quantum effects such as confinement and tunneling have played a significant role in device characteristics. In this work, we have investigated quantum ballistic transport properties of Si nanowire MOSFET (Si NWMOSFET) with 4 nm gate length. Since gate length is shorter than the electron wavelength in our Si NWMOSFET, ballistic transport in one dimension (1D) is expected to be the dominant mechanism for carrier transport. Therefore, the parameters which are crucial for efficient MOSFET operation such as gate length, temperature, gate voltage have been simulated using the density gradient method to present quantum confinement effect on device transfer characteristics. We have found that Si NWMOSFET has an I_on/I_off ratio > 10^8, which is close to ideal value for similar nano MOSFETs. Moreover, due to short channel, intersubband scattering can deteriorate 1D ballistic transport properties of Si NWMOSFET, especially in low temperatures.

Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs

An Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed that, when the IG is negligible, there is a trade-off between the DC open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si NW MOSFET OTA presented the lowest AV0 (52 dB) but the largest GBW (9.5 MHz). The largest gain was obtained by the Si NW TFET (97 dB) but it also presents the lowest GBW (30 kHz). The SiGe-source TFET stands in the middle, with an AV0 of 88 dB and a GBW of 715 kHz. However, when IG is not negligible and included in the model, the gain of the TFET OTAs decreases considerably, down to 38.3 dB in the case of the Si TFET and down to 52.6 dB in the case of the SiGe-source TFET. This decrease in gain is mostly caused by an alteration in the desired bias point in the second stage of the OTA due to the change of the output voltage and bias currents. This issue possibly can be mitigated by using circuit design strategies. Nevertheless, the SiGe-source TFET OTA is less impacted by the gate current than the Si TFET OTA and still presents a larger gain than the Si NW MOS OTA (52.6 dB against 50 dB) when the IG is considered.

3-D Full-Band Monte Carlo Simulation of Hot-Electron Energy Distributions in Gate-All-Around Si Nanowire MOSFETs

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current-voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices.

Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length

In this work, drain current ID for 7-nm gate length dual-material (DM) cylindrical gate all around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Schrodinger's equation with Poisson’s equation. The splitting of conduction in multiple sub-bands has been considered and there is no doping in the channel region. The effect of DM gate engineering (variation of screen gate and control gate length having different work function) for SiNW channel with 2-nm radius and gate oxide (SiO2) thickness of 0.8 nm on ID have been studied. It was found that DM gate engineering reduces drain-induced barrier lowering (DIBL) but it also slightly increases sub-threshold slope (SS). This work has obtained small DIBL (~54 mV/V), small SS (~68 mV/dec), and higher IOn/IOff (~4 × 108) ratio as compared to literature concerning the inversion mode devices. The smallest DIBL is obtained when control gate length is the highest, and vice versa. With increase in control gate length, there is also increase in both IOn and IOff but IOn/IOff ratio decreases.

Impact of Source to Drain Tunneling on the Ballistic Performance of Si, Ge, GaSb, and GeSn Nanowire p-MOSFETs

We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge 0.96 Sn 0.04 nanowire MOSFETs (NWFETs) were simulated at a scaled gate length (L G ) of 10 nm, using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence band, the k·p method was used. For each material, we simulated a set of six different transport/confinement directions, at a fixed OFF-state current (I OFF ) of 100 nA/μm and supply voltage V DD = -0.5 V to identify the direction with the highest ON-current (I ON ). For Ge, GaSb, and GeSn [001]/110/110 oriented NWFETs, with [001] being the direction of transport and 110, 110 being the directions of confinement for the nanowire, showed the best ON-state performance, compared to other orientations. Our simulation results show that, despite having a higher percentage of SDT in OFF-state than silicon, GaSb [001]/110/110 NWFET can outperform Si NWFETs. We further examined the role of doping in limiting SDT and demonstrated that the ON-state performance of Ge and GeSn NWFETs could be improved by reducing the doping in the source/drain (S/D) extension regions. Our simulation result show that with properly chosen channel transport orientation and S/D doping concentration, performance of materials with high hole mobility can be optimized to reduce the impact of SDT and provide a performance improvement over Si-channel based p-MOSFETs.

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level.

Subthreshold Kink Effect Revisited and Optimized for Si Nanowire MOSFETs

A device design technique for boosting nanowire MOSFET performance beyond a 10-nm technology node is proposed using physical modeling and 3-D numerical simulation. The revisited subthreshold kink effect improves the transistor ON–OFF current ratio and is achievable with supply bias lower than 1 V. The proposed technique overcomes the fundamental and thermal voltage-limited subthreshold swing (SS). An optimized device design methodology to exploit the lowered SS is provided as well.

Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability

In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire mosfet (NWFET)-based 6-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with $V_{{\rm DD}}$ downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with $V_{{\rm DD}}$ downscaling, similar to the hold SNM experimental data reported in the literature for Si GAA NWFET-based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.

Future of nano CMOS technology

Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end.The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9nm in production.However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

Demonstration of higher electron mobility in Si nanowire MOSFETs by increasing the strain beyond 1.3%

In this work we demonstrate the benefit of high uniaxial tensile strain on the performances of Si nanowire (NW) MOSFETs. High uniaxial tensile strained Si NWs were realized by exploiting a “bridge technology” based on patterning of an initial biaxial tensile strained Si on insulator (sSOI) into thin NWs with large pads. Strain relaxation on the large pads amplifiers the strain in the NWs. Strained Si NW-arrays along 〈110〉/(100) direction with tensile strain values up to 2.2% were achieved. We have fabricated n-type Si NW-array MOSFETs with HfO2/TiN gate stack and NiSi2 source/drain contacts. An increase of Ion current by a factor of 1.35 was observed then the uniaxial strain was increased from 1.3% to 1.8% in NW MOSFETs. The enhanced device performance is primarily attributed to a higher electron mobility in the highly strained Si NWs.

Surrounding gate long channel nanowire MOSFET modelling—extended analysis

Based on the approximate solution of Poisson’s equation in the case of a p-doped silicon body, an improved current-voltage characteristic model of long-channel cylindrical surrounding-gate Si nanowire MOSFET is proposed. The improvement itself considers a realistic description of the carriers’ mobility degradation owing to the radial electric field and a more detailed and accurate analytical solution to the 1D Poisson’s equation than the solutions available in the literature. The model is valid in the wide range of the doping concentration and shows a satisfactory level of agreement with the two-dimensional simulation results and the former models. It can also be applied to different operation regimes such as subthreshold, linear and saturation regimes.

Impact of series resistance on Si nanowire MOSFET performance

In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by dividing it into five resistance components namely spreading resistance, extension resistance, interface resistance, deep source-drain resistance and contact resistance. The model is validated using 3-D device simulations of 22 nm GAA devices with Source/Drain extension (SDE) length of 15 nm to 35 nm, diameter of 8 nm to 16 nm and oxide thickness of 10 A to 40 A for both n-FET and p-FET. It is found that the spreading resistance due to lateral doping gradient contributes significantly to the total series resistance. Further, the dependence of NW device performance on series resistance is quantitatively investigated with change of diameter, SDE length and Source/Drain (S/D) implantation dose. Results show a strong NW device performance dependence on S/D doping profile and extension length defining a design trade-off between Short Channel Effects (SCEs) and series resistance. It is seen that the increase in series resistance due to increase of extension length or decrease of implantation dose beyond a certain limit reduces the device drive current significantly with nearly constant OFF-state leakage current. Hence, optimization of extension length and S/D implant dose is an important device design issue for sub 22 nm technology nodes.

Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80nm Si cores on bulk Si using [email protected] optical lithography and local oxidation for the first time. 0.833GPa uniaxial tensile stress is measured in the buckled suspended dual Si nanowires using micro-Raman spectroscopy. The array of GAA buckled dual Si nanowire MOSFETs at VDS=50mV shows 64mV/dec. subthreshold slope and 61% stress-based low-field electron mobility enhancement in comparison to the omega-gate relaxed reference device. Finally, digital logic implementation is demonstrated using multi-gate nanowires on bulk Si.

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> , 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> , and 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate oxide thickness ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0 V; <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">acc</sup> /(CW <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ), in strong accumulation regime.

A continuous current model of ultra-thin cylindrical surrounding-gate inversion-mode Si nanowire nMOSFETs considering a wide range of body doping concentration

Based on the approximated solution of Poisson's equation, we propose a continuous current model of ultra-thin fully depleted cylindrical surrounding-gate Si nanowire MOSFETs. It matches well with three-dimensional simulation results using SILVACO Atlas TCAD in a wide range (from intrinsic to high doping) of the body doping concentration without any empirical fitting parameters. It is valid for all the operation regions such as subthreshold, turn-on, linear and saturation.

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

In this paper, we report for the first time making multi-gate buckled self-aligned dual Si nanowires including two sub-100 nm cross-sectional cores on bulk Si substrate using optical lithography, hard mask/spacer technology, and local oxidation. ≈0.8 GPa uniaxial tensile stress was measured on the buckled dual nanowires using micro-Raman spectroscopy. The buckled multigate dual Si nanowires show excellent electrical characteristics, e.g., 62 mV/decade and 42% low-field electron mobility enhancement due to uniaxial tensile stress in comparison to the non-strained device, all at VDS = 50 mV and 293 K.

(Invited) Low-Frequency Noise Reduction in Si Nanowire MOSFETs

We have investigated the noise spectral density of nanowire and planar FETs. It was experimentally found that the nanowire FET shows lower noise density than the planar FET. By a simulation using Poisson-Schrödinger equations, the distribution of inversion carriers is located further from the interface due to quantum confinement, which well explains the observed lower noise density of nanowire FET.

Low-frequency noise reduction in Si Nanowire MOSFETs

not Available.