Si Nanowire MOSFETs Research Articles

Comparisons of Performance Potentials of Si and InAs Nanowire MOSFETs Under Ballistic Transport

In this paper, we study the band structures of Si and InAs nanowires based on a first-principles calculation and project performance potentials of Si and InAs nanowire field-effect-transistors (NWFETs) by using a semiclassical ballistic transport model. We demonstrate that the device performance of InAs NWFETs strongly depends on its cross-sectional dimension and gate oxide thickness. In particular, InAs NWFETs unexpectedly indicate lower current drivability than Si NWFETs as the gate oxide thickness is extremely scaled down to 0.5 nm in the ballistic limit. We discuss the mechanism in terms of operation in quantum capacitance limit (QCL). We also demonstrate that the advantage in the lower power operation with InAs NWFETs reduces when the devices operate in the QCL or higher subbands with a heavier transport effective mass participate in the transport.

Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation.

Analysis of Carrier Transport in Trigate Si Nanowire MOSFETs

Trigate Si nanowire (NW) MOSFETs have been fabricated and characterized at temperature between 77 and 300 K in the dark and under light pumping. The NW width <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> and height <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> , the gate length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> , and the gate oxide thickness <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> , respectively, were 7-25, 16, 34-52, and 7 nm. The interesting aspects of Si NW MOSFETs with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> = 25 nm /52 nm, 24 nm/34 nm, 7 nm/47 nm, and 10 nm/37 nm measured at low drain voltage are that the drain current exhibited not only inverse temperature dependence in strong accumulation but also clear current plateaus/oscillations near the threshold regime at temperature up to 300 K. Notably, such current plateaus diminished or were invisible in the device of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> = 24 nm/42 nm. The observed current behaviors are inferred from the interplay of quantum interference and intersubband scattering effects. Additional current plateaus due to photogenerated excitons were also observed in the studied devices, evidencing photoexcitation effects on quantum transports through a Si NW.

Variability in Si Nanowire MOSFETs Due to the Combined Effect of Interface Roughness and Random Dopants: A Fully Three-Dimensional NEGF Simulation Study

In this paper, we study the impact of surface roughness and its combination with random discrete dopants on the current variability in nanometer-scale nanowire metal-oxidesemiconductor field-effect transistors. It is shown that these two variability sources cannot be regarded as independent in their effect on transport. Interface roughness results in body thickness fluctuations and scattering, which degrades transistor performance. This paper extends our previous study, in which we concentrated only on the impact of random discrete dopants in the source/drain regions in the same type of devices that lead to current variability. We have simulated ensembles of 30 devices, which differ due to the physical manifestation of the variability sources, including the detailed microscopic pattern of the interface in the channel and the number and configuration of discrete dopants in the source/drain regions. An ensemble of devices, with rough interfaces and continuous doping, has first been simulated to differentiate the effect of the interface roughness from the random discrete dopants before considering the combined case. It was found that, in some peculiar cases, the surface roughness induced resonant structures inside the device, producing quasibound states. These resonant states are similar to those related to individual discrete dopants in our previous study. We found that there is strong correlation between the microscopic patterns of the interface and the device performance due to the non-self-averaging of the microscopic features, which plagues devices with small channel lengths. The surface roughness induces a threshold voltage shift and decreases the ON-current of the device due to scattering. In the fully 3-D nonequilibrium Green's function formalism, both effects are combined in the propagation of the electron wave through the device. We have extracted the surface roughness related scattering contribution and estimated the associated mobility.

Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs

In this paper, we demonstrate analytical device models and a unique subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current characteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with numerical devices from ambipolar thermionic tunneling to unipolar drift-diffusion and a combination of both as the dopant segregation doping and thickness are varied. The convex curvature in the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> characteristics is accurately reproduced by the subcircuit compact model, and it is shown for the first time that such a unique g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> characteristic in DSS devices is only feasible to be modeled by the subcircuit approach.

Current Variability in Si Nanowire MOSFETs Due to Random Dopants in the Source/Drain Regions: A Fully 3-D NEGF Simulation Study

In this paper, we study the impact of random discrete dopants in the source/drain (S/D) leads on the current variability of a gate-all-around Si nanowire transistor. Due to the strong inhomogeneities of the self-consistent electrostatic potential, a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fully</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3D</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">real-space</i> nonequilibrium Green's function (NEGF) formalism is used. N-channel transistors with random discrete donors in the S/D regions varying in both numbers and locations have been simulated. We have studied the impact of quasi-bound (QB) states and transmission resonances associated with the attractive potential of the donors on the screening of the impurities and on the current transport. The convergence of the coupled 3D Poisson-NEGF equations for narrow wires with discrete dopants is cumbersome due to the quasi-discrete nature of QB states and resonances of the attractive impurity potential. We present a robust solution strategy dealing with the convergence challenges. Large variations in the on-current and modest variations in the subthreshold slope are observed in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> characteristics when comparing devices with microscopically different discrete dopant configurations. We have also estimated the access resistance associated with the random dopant regions in the source and the drain leads and find very good agreement with the resistance estimated from the bulk silicon mobility at the same doping concentration.

Roadmap for 22 nm and beyond (Invited Paper)

The down-scaling is still the most important and effective way for achieving the high-performance logic CMOS operation with low power, regardless of its concern for the technological difficulties, and thus, the past shrinking trend of the gate-length has been very aggressive. In this paper, logic CMOS technology roadmap for ‘22 nm and beyond’ is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The future gate-length shrinking trend predicted in the past several versions of the ITRS has been too aggressive even for the most advanced semiconductor companies to catch up, and thus, the predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Corresponding to this, the pace of the introduction of new technologies becomes slower. For the long term, the limit of the downsizing is a big concern. The limit is expected to be at the gate length of around 5 nm because of the too huge off-leakage current in the entire chip. Until that we will have probably six more generations or ‘technology nodes’, considering that we are now in the so-called 45 nm generation. It would take probably 20–30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system such as the brains of insects and even human will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.

Monte Carlo study of coaxially gated CNTFETs: capacitive effects and dynamic performance

Carbon nanotubes (CNT) appear as a promising candidate to shrink field-effect transistors (FET) to the nanometer scale. Extensive experimental works have been performed recently to develop the appropriate technology and to explore DC characteristics of a carbon nanotube field effect transistor (CNTFET). In this work, we present results of a Monte Carlo simulation of a coaxially gated CNTFET, including electron–phonon scattering. Our purpose is to present the intrinsic transport properties of such material through the evaluation of the electron mean-free-path. To highlight the potential of the high performance level of CNTFET, we then perform a study of the DC characteristics and of the impact of capacitive effects. Finally, we compare the performance of CNTFET with that of a Si nanowire MOSFET. To cite this article: H. Cazin d'Honincthun et al., C. R. Physique 9 (2008).

Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

고감도 이미지 센서용 실리콘 나노와이어 MOSFET 광 검출기의 제작

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a <TEX>$1.5{\mu}m$</TEX> resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.