Abstract
A device design technique for boosting nanowire MOSFET performance beyond a 10-nm technology node is proposed using physical modeling and 3-D numerical simulation. The revisited subthreshold kink effect improves the transistor ON–OFF current ratio and is achievable with supply bias lower than 1 V. The proposed technique overcomes the fundamental and thermal voltage-limited subthreshold swing (SS). An optimized device design methodology to exploit the lowered SS is provided as well.
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