A non-uniform silicon TFET design with dual-material source and compressed drain

Abstract

Tunnel FET is the well-built candidate in the field of low-power ICs mainly because of its lower subthreshold swing (SS). But its ON current is relatively small and ambipolar current is high. The advantage of having a lower SS does not hold for higher gate voltages, which leads to higher average SS. In this paper, for the first time, a non-uniform channel with double-material source and compressed drain TFET structure is introduced. The simulation results show that the proposed structure has a minimum point SS of 9 mV/decade and an average SS of 22 mV/decade for a wide range of gate voltages. In addition, the ambipolar current, ON current, and OFF current are obtained to be 10−14 A/μm, 10−5 A/μm, and 10−16 A/μm, respectively, which lead to a remarkable value of the ON–OFF current ratio of about 1011. The effects of trap charge at oxide/semiconductor interface for different trap charge distributions have been investigated. Finally, it is observed that as compared to uniform distribution traps, Gaussian distribution traps degrade the characteristics in terms of ON–OFF current ratio and SS.