A New Z-Shaped Gate Line Tunnel FET with Improved Electrostatic Performance

Abstract

In this paper, we simulated a new line tunnel field-effect transistor (TFET) with a Z-shaped gate. The proposed Z-TFET generates vertical tunneling due to the presence of the front gate over the entire source region. This generates faster tunneling between the source and the channel region, providing a 3-decade improvement in drain current compared to conventional DG-TFET. The ambipolar current is also improved by 1-decade with a subthreshold swing (SS) of 40 mV/decade (reduces by 18%). Further optimization of the front and back gate is performed to investigate its impact on the analog performance of Z-TFET. The simulated results exhibit improvement in ambipolar current, reduction in OFF current by optimizing the back-gate length. This simulation work is performed in the presence of field-induced quantum confinement using the TCAD device simulator. Additional reliability issue of the structure in the presence of the interface trap charge at the semiconductor-oxide interface is properly investigated. The effect of trap charge density (Nf) and capture cross-section (σ) variation on the transfer characteristics and average SS has been examined. The proposed device can provide a higher ION/IOFF of 1013 and ION/IAMB of 107.