Investigation of Planar and Double-Gate Junctionless Transistors with Non-Uniform Doping

Abstract

In this paper for the first time we present the comparative electrostatic behavior analysis of Junctionless Transistor (JLT) with non-uniform doping profile in the vertical direction. Two structures, planar (single gate) JLT in silicon-on-insulator (SOI) and double gate JLT (DG-JLT) are used for 2-D quantum transport simulation. Position of peak concentration of impurities has been varied across channel to get less leakage current, better sub-threshold swing. Reduced OFF current, subthreshold swing and High ON to OFF current ratio are achieved in JLT (Planar and double-gate structure) by tuning shape and peak of non-uniform doping profile. Peak concentration of impurities at the surfaces gives the better performance in terms of reduced OFF current, subthreshold swing and High ON to OFF current ratio. Moreover it is observed that multi-gate structure with nonuniform doping profile will give robust design compared to the single-gate structure with non-uniform doping profile.