Si LSIs Research Articles

(Invited) Display and LSI Applications of Oxide Semiconductor LSIs (OS LSIs) Using Crystalline In–Ga–Zn Oxide (IGZO): Applications Related to Coronavirus COVID-19 Pandemic

The coronavirus COVID-19 pandemic is becoming a global crisis in 2020. Global climate change is an indirect cause of the spread of infectious diseases [1]. The increase in greenhouse gas as a result of increased power consumption has an adverse effect on this climate change. The amount of power consumption continues to increase as human society advances, and Japan Science and Technology Agency’s report says that global and Japan’s annual power consumption concerning IT equipment in 2050 will be nearly 200 times as large as the present global and Japan’s total annual power consumption.” [2]. This means that one of the main causes of the global climate change would be the increase in the amount of power consumption through the spread of fast-growing Internet of Things (IoT) and artificial intelligence (AI) technologies.An anwer to the question of how to reduce power consumption and defend against infectious diseases that may threaten human beings while developing the IoT and AI technologies is to reduce the power consumption of semiconductor devices intensely and reduce the power consumption concerning IT equipment to 1/1000 of the present power consumption.A field-effect transistor (FET) fabricated using a c-axis aligned crystalline In–Ga–Zn oxide (CAAC-IGZO), which is a typical example of crystalline oxide semiconductor (OS) ceramics, exhibits an off-state current I off in the order of yA/mm (10- 24 A/mm) at 85°C [3,4]. The FET we developed is a FinFET with a trench-gate self-aligned (TGSA) structure [5].As shown in the figure, the upper limit of operation efficiency of AI accelerators fabricated using Si LSIs is 10 TOPS/W, whereas normally-off CPUs [6,7] and AI accelerators fabricated using CAAC-IGZO could achieve an operation efficiency of 100 TOPS/W (8 bits) or 1 POPS/W (1 bit). If this technology is adopted in all VLSI devices and supercomputers, reducing the power consumption of those devices by 1000 times will come closer to reality even in the AI/IoT era. Therefore, we believe that the use of the CAAC-IGZO technology is the only solution to the global climate change.OS LSIs are applicable to all kinds of displays including displays for augmented reality and virtual reality, dynamic random access memories, and 3D OS NANDs (3D NANDs fabricated using IGZO). This work introduces crystalline IGZO ceramics, which would be a future key technology, and LSI and display applications of LSI of the crystalline IGZO ceramics.

이중연료엔진의 연료가스공급시스템에 대한 안전무결도 기반 안전계장시스템 설계

In this study, the shutdown system of the fuel gas supply system is designed based on the Safety Integrity Level of IEC 61508 and IEC 61511. First of all, the individual risk(/year) and the risk matrix which are the risk acceptance criteria are set up for the qualitative risk assessment such as the HAZOP study. The natural gas leakage at the gas supply pipe is identified as the highest risk among the hazards identified through the HAZOP study and as a safety instrumented function the shutdown function for leakage was defined. SIL 2 and PFD() for the shutdown function are determined by the layer of protection analysis(LOPA). The shutdown system(SIS) carrying out the shutdown function(SIF) is verified and designed according to qualitative and quantitative requirements of IEC 61508 and IEC 61511. As a result of SIL verification and SIS conceptual design, the shutdown system is composed of two gas detectors voted 1oo2, one programmable logic solver, and two shutdown valve voted 1oo2.

(Invited) Challenges of Si Photonics for Photonics Integration on Si LSIs

The first generation of Si photonics is about over by breakthrough of n+Ge laser as a on-chip monolithic light source. The grand challenge for the next generation is to implement on-chip wavelength division multiplexing (WDM); how to lock the wavelength on an uncooled chip. The present paper proposes the key to the locking in terms of strain to control refractive and absorption indices.

Challenges of Si Photonics for Photonics Integration on Si LSIs

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Analysis of the Hysteresis Behavior in Poly-Si TFTs Using On-the-Fly Measurement

The hysteresis behavior in p-type poly-Si TFTs causes malfunctions in analog circuits. To analyze the hysteresis, we adopted the On-the-Fly measurement that was used in the analyses of the negative bias temperature instability of Si LSIs. We modified the measurement for poly-Si TFTs and monitored the hole trapping from the fully detrapped states in order to quantitatively evaluate the hysteresis. A TFT annealed at 550oC had smaller trapping than a TFT annealed at 490oC due to fewer Si-OH bonds.

Silicon Photonics for Optical Interconnection

The present paper reviews recent advances of system applications of on-chip optical interconnections in terms of Si Photonics to overcome “heat penalty” in Si LSIs.

Twisted Differential Transmission Line Structure for Global Interconnect in Si LSI

This paper investigates the twisted differential transmission line structure to achieve high-speed signal transmission and electromagnetic interference (EMI) noise reduction of global interconnects in Si LSIs. The differential transmission line in Si LSIs can transmit a 12 Gbps pulse signal and has the capability of reducing EMI noise. The proposed twisted-diagonal-pair line provides high-speed, low-EMI-noise, high-crosstalk-robustness and high-density global interconnects in Si LSIs.

Fabrication and current-drive of SiGe/Si ‘Micro-origami’ epitaxial MEMS device on SOI substrate

A micromirror structure with SiGe/Si heteroepitaxial layer on a silicon-on-insulator (SOI) substrate using a ‘Micro-origami’ technique has been successfully fabricated. The micromirror is supported by two curved hinge structures. The device is driven by application of a current, and net angular displacements larger than 10° (static) and 30° (in resonance) were obtained. These values are comparable with or even larger than the reported values for other MEMS optical switches or beam scanning devices. The experimental results suggest that the movement is evoked by a thermal effect. The Micro-origami device has advantages of low operation voltage smaller than 2 V, and structural compatibility with the Si or SiGe LSIs.

Measurement of process-induced defects in Si sub-micron devices by combination of EDMR and TEM

Process-induced defects are a serious issue for modern sub-micron Si LSIs. To characterize such defects, two different techniques are useful: electrically detected magnetic resonance (EDMR) and transmission electron microscope (TEM), which can detect small (point) and extended defects, respectively. We applied EDMR and TEM to the issue of defect-induced leakage currents in dynamic-random-access memory (DRAM) cells. For our DRAM samples (a 0.25-μm-rule series), although TEM showed no extended defects, EDMR successfully detected two types of point defects: V 2 +O x (Si divacancy-oxygen complexes) and larger Si vacancies (at least larger than V 6 ). We confirmed that these defects are the source of DRAM leakage currents. The observed defects were formed by ion implantation processes, but were more thermally stable than those in bulk Si crystals. The origins of this enhanced stability are attributed to the presence of oxygen atoms and a strong mechanical strain in LSIs. To clarify the origin of the complicated strain in LSI structures, we can directly measure the local-strain distribution in DRAM samples by means of convergent-beam electron diffraction (CBED) using TEM, which provides us with a valuable hint for understanding the formation mechanism of process-induced defects.

Electrically detected magnetic resonance of ion-implantation damage centers in silicon large-scale integrated circuits

We used electrically detected magnetic resonance to study the microscopic structure of ion-implantation-induced point defects that remained in large-scale Si integrated circuits (Si LSIs). Two types of defects were detected in the source/drain (n+-type) region of 0.25-μm-gate-length n-channel metal oxide semiconductor field-effect-transistors on LSIs: (i) a spin-1 Si dangling-bond (DB) pair in divacancy–oxygen complexes (DB–DB distance, R≈0.6 nm); and (ii) a series of larger Si vacancies involving distant Si DBs (R⩾1.4 nm). These vacancy-type defects were much more thermally stable in Si LSIs than those in bulk Si crystals. We suggested two physical mechanisms for this enhanced stability: internal mechanical stress and oxygen incorporation in the active regions of LSIs. After examining the relationship between the defects and current–voltage characteristics, we concluded that these defects are distributed in the near-surface n+-type region close to the gate and that they are the source of the gate-induced drain leakage currents.

Wafer bonding technology for optoelectronic integrated devices

Wafer bonding has been investigated as a key technology to integrate InP lasers on Si for optoelectronic integrated circuits. The bonding process has been optimized to allow the integration of InGaAsP/InP double-heterostructures (DHs) on Si with keeping the crystal qualities good enough to realize the lasers. As a result, room temperature continuous-wave (CW) operation of InP edge-emitting lasers has been achieved. In addition, as one of the building blocks to implement the optimal interconnections between Si LSIs, InP optical devices on Si integrated with the back-surface diffractive lenses have been demonstrated. A novel bonding process which allows an integration on structured wafers, such as Si LSI wafers, has also been proposed. The wafer bonding is thought to be a promising technique to implement optical interconnections between Si LSI chips.

Si LSI Process Technology for Integrating Ferroelectric Capacitors

The fabrication procedure of ferroelectric thin film capacitors onto conventional Si LSIs is investigated. Electrical characteristics of the integrated Ba1-x Srx TiO3 (BST) capacitors and the metal-oxide-semiconductor transistors embedded in the Si substrate are examined. Results of these measurements suggest the usefulness of this integration process for the fabrication of ferroelectric thin film devices, which is substantiated by the evaluation of an analog/digital IC with the integrated BST bypass capacitor.

Panel Discussion; Performance Limitation of Si, III-V and Josephson Junction LSIs

Panel Discussion; Performance Limitation of Si, III-V and Josephson Junction LSIs Chairman: T. Sugano. Co-chairman: Y. Okuto. Panel Members: A. Anzai, S. Hasuo, S, Kohyama, J. Matisoo, M. Ohmori.