Si Chip Research Articles

Pressureless Sintered-Silver as Die Attachment for bonding Si and SiC Chips on Silver, Gold, Copper, and Nickel Metallization for Power Electronics Packaging: The Practice and Science

Low-temperature silver (Ag) sintering is emerging as a cutting-edge die-attach technology for power electronics packaging. However, the industry still has concerns about completely accepting this technology. One of the reasons is a lack of knowledge about the mechanism and process of sintered silver bonding on various metallization. Before, we reported a preliminary assessment of the die-shear strength and microstructures of Si dummy device attached on Ag, Au, and Cu metallization. This research will go deeper into the practice and science of attaching Si and SiC devices with sintered-Ag on substrates with up to seven most widely used metallizations, including electroplated Ag, Ni/Au, and Ni, electroless-plated Ni(P)/Ag, Ni(P)/Au, and Ni(P), and native Cu on DBC substrate. All sintered-Ag die-attach were pressureless in the air at temperatures ranging from 220 °C to 300 °C. The mechanical, electrical, and thermal parameters, as well as the microstructural analyses, were assessed. The purpose of this research is to gain a better understanding by: 1) discussing effects of devices and substrate metallizations on the mechanical, electrical, and thermal characteristics; 2) reviewing fundamental mechanisms of interfacial adhesion for sintered-Ag bonding, and 3) providing practical considerations for developing Si and SiC sintered-Ag die-attaching profiles on the widely used substrate metallization.

Thermal response of active Si in press-fit rectifier diodes by confocal Raman microscopy: Influence of diode design and technology

Overheating resulting from the circulation of high electric currents (in the order of tens of amperes) that some electronic devices undergo when they are in operation, can induce structural modifications such as mechanical stresses that could reduce their lifetime. In order to optimize their performance, understanding the phenomenology that takes place in devices at high-temperature regimen induced under operating conditions is fundamental. In this work, the thermal behavior of the Si-based semiconductor part of several press-fit rectifier diodes with different design and technology (Schottky, Metal Oxide Semiconductor and PN junction) has been studied by Confocal Raman Microscopy. The experiments have been performed on two specific functional parts of the active Si chip (i.e., near and far from the Si/electrode interface), discerning non-thermal effects such as stress and doping from the purely thermal ones with a specific analysis procedure of the Si T2g Raman active mode. This methodology enables an advance, non-destructive and located characterization of the thermal response of the diodes, which will help to optimize the performance of electronic devices and extend their useful life and reliability by avoiding or, at least, minimizing the damage caused by the temperature excess.

Integrating porous silicon layer backing to capacitive micromachined ultrasonic transducers (CMUT)-based linear arrays for acoustic Lamb wave attenuation

Lamb waves propagating in the substrate of linear arrays integrated on a silicon (Si) chip may degrade the elementary performances of the imaging device. In fact, these waves are radiated in the imaging medium. Their superimposition with the relevant ultrasonic signals alters the image performances (i.e., lateral and axial resolutions). In this article, we investigate the interest of using a thin layer of porous silicon (PS) as an absorbing material, aiming to reduce the total device dimensions compared to more traditional backing materials and facilitate device integration with on-chip electronics. The proposed method was applied to Capacitive Micromachined Ultrasonic Transducers. To this purpose, a PS layer with a thickness of 60 μm and a porosity of 50% was etched on the rear side of a 256-elements linear array. The electroacoustic response of the elements integrated on the Si substrate was compared to those on the Si/PS substrate, showing no deterioration of the acoustic characteristics (i.e., center frequency and bandwidth) after PS layer fabrication. To assess the PS silicon layer influence on Lamb wave attenuation, acoustic cross-talks were measured for each array element. The radio-frequency dataset was used to determine the dispersion curves of Lamb waves in the substrate. The comparison between the two substrates showed a significant attenuation value (superior to 30 dB) of Lamb waves induced by the PS layer.

Coherent generation of arbitrary first-order Poincaré sphere beams on an Si chip.

Generalized vector vortex light beams possess spatially variant polarization states, and higher-order Poincaré spheres represent a powerful analytical tool for analyzing these intriguing and complicated optical fields. For the generation of these vortex beams, a range of different methods have been explored, with an increasing emphasis placed on compact, integrated devices. Here, we demonstrate via numerical simulation, for the first time, an on-chip light emitter that allows for the controllable generation of all points on a first-order Poincaré sphere (FOPS). The FOPS beam generator consists of a waveguide-coupled, nanostructured Si microring resonator that converts two guided, coherent light waves into freely propagating output light. By matching their whispering gallery modes with the nanostructures, the fundamental TE (transverse electric) and TM (transverse magnetic) input modes produce radial and azimuthal polarizations, respectively. These two linear polarizations can form a pair of eigenstates for the FOPS. Consequently, tuning the phase contrast and the intensity ratio of these two coherent inputs allows for the generation of an arbitrary point on the FOPS. This result indicates a new way for on-chip vector vortex beam generation, which may be applied for integrated optical tweezers and high-capacity optical communications.

Intermetallic compound formation and growth behavior at the interface between indium and Au/Ni(V) metallization

Pure indium (In) solder is promising as the thermal interface material (TIM) for efficient heat dissipation and as the Pb-free solder for cryogenic joining applications. In this study, liquid/solid and solid/solid reactions between In and Au/Ni(V) surface finish on a Si chip are investigated to explore the formation of intermetallic compounds (IMCs) formed at the In/Au/Ni(V) interface and their growth kinetics. Two IMCs, (Ni,Au)28In72 and Ni-V-In, are formed at the interface in the liquid/solid and solid/solid reactions performed at 220–260 °C and 100–150 °C, respectively. The growth of the (Ni,Au)28In72 crystalline phase follows the parabolic law and the underlying Ni-V-In amorphous phase is formed as a result of phase transformation from original Ni(V) due to outward diffusion of Ni and inward diffusion of In. This phase transformation proceeds at a faster rate in the liquid/solid reaction. The Ni supply is exhausted once the Ni(V) is completely transformed into the Ni-V-In phase, accelerating the ripening reaction of (Ni,Au)28In72 and its spallation into the molten In matrix.

Towards Transient Electronics through Heat Triggered Shattering of Off-the-Shelf Electronic Chips.

With most of the critical data being stored in silicon (Si) based electronic devices, there is a need to develop such devices with a transient nature. Here, we have focused on developing a programmable and controllable heat triggered shattering transience mechanism for any off-the-shelf (OTS) Si microchip as a means to develop transient electronics which can then be safely and rapidly disabled on trigger when desired. This transience mechanism is based on irreversible and spontaneous propagation of cracks that are patterned on the back of the OTS chip in the form of grooves and then filled with thermally expandable (TE) material. Two types of TE materials were used in this study, commercially available microsphere particles and a developed elastomeric material. These materials expand >100 times their original volume on the application of heat which applies wedging stress of the groove boundaries and induces crack propagation resulting in the complete shattering of the OTS Si chip into tiny silicon pieces. Transience was controlled by temperature and can be triggered at ~160–190 °C. We also demonstrated the programmability of critical parameters such as transience time (0.35–12 s) and transience efficiency (5–60%) without the knowledge of material properties by modeling the swelling behavior using linear viscoelastic models.

Ultrafast photoresponse of vertically oriented TMD films probed in a vertical electrode configuration on Si chips.

Integrated photodetectors based on transition metal dichalcogenides (TMDs) face the challenge of growing their high-quality crystals directly on chips or transferring them to the desired locations of components by applying multi-step processes. Herein, we show that vertically oriented polycrystalline thin films of MoS2 and WS2 grown by sulfurization of Mo and W sputtered on highly doped Si are robust solutions to achieve on-chip photodetectors with a sensitivity of up to 1 mA W−1 and an ultrafast response time in the sub-μs regime by simply probing the device in a vertical arrangement, i.e., parallel to the basal planes of TMDs. These results are two orders of magnitude better than those measured earlier in lateral probing setups having both electrodes on top of vertically aligned polycrystalline TMD films. Accordingly, our study suggests that easy-to-grow vertically oriented polycrystalline thin film structures may be viable components in fast photodetectors as well as in imaging, sensing and telecommunication devices.

A 4 × 4 Biosensor Array With a 42-μW/Channel Multiplexed Current Sensitive Front-End Featuring 137-dB DR and Zeptomolar Sensitivity

This paper presents a multiplexed current sensitive readout for label-free zeptomolar-sensitive detectors realized with large area Electrolyte Gated Organic Thin Film Transistors (EGOFETs). These highly capacitive biosensors are multiplexed using an OTFT line driver and OTFT switches, and interfaced to a 65-nm Si CMOS, low power, pA-sensitive front-end. The Si chip performs analogue-to-digital conversion and data transmission to a microcontroller too. A current domain interface is used to transmit the signals coming from multiple biosensors to the 1.2 V-supply CMOS Si-IC via the 30V-supply OTFT electronics. Exploiting an analogue module implemented in the Si-IC, the EGOFETs are precisely biased, even in presence of a large OTFT multiplexer resistance. The CMOS current sensitive front-end achieves a dynamic range (DR) of 137 dB and a power consumption of 42 lW per channel reaching a state-of-the-art DR-power-bandwidth FOM of 208 dB. The front-end has been designed with a first stage programmable-gain, active-feedback transimpedance amplifier topology that, contrary to common current-sensitive front-end solutions, is not affected by the sensor capacitance. The system has been validated with different concentrations of human IgG and IgM proteins using both a single sensor and a 4x4 array of EGOFETs. Thanks to the multiplexing strategy and the low-costs of its modules, the system here presented has the potential to enable widespread use of precision diagnostic with extreme sensitivity even in point-of-care and low-resource settings.

Solid-Liquid Interdiffusion Bonding between Ti/Ni/Ag/Sn Backside Metallized Si Chips and Cu/Al2O3 - DBC Substrates with Au/Pd/Ni Surface Finish

Solid-Liquid Interdiffusion Bonding between Ti/Ni/Ag/Sn Backside Metallized Si Chips and Cu/Al₂O₃ - DBC Substrates with Au/Pd/Ni Surface Finish

Application of Modified Strain Hardening rule for thermal fatigue evaluation of Al Wire Bonding in Power Module

Power modules are key products used in various fields such as home appliances, information equipment, factory equipment, and transportation equipment. Research on power modules with long life and high reliability will greatly contribute to the realization of a low-carbon society. As an example, we considered an IGBT (Insulated Gate Bipolar Transistor). An important part of this is the joint between the wire and the semiconductor chip. Failure occurs at this joint due to repeated thermal loads due to operation of the power device. In this study, we focused on the wire lift-off phenomenon in which the Al wire separates from the Si chip due to thermal fatigue at the Al-Si joint, and thermo-elastic-plastic creep analysis of the crack tip is performed using the FEM mode. Regarding the influence of modified strain hardening of Al on thermal fatigue, the evaluation parameter ΔWin was investigated and report.

High-Resolution Multi-Isotope Imaging Mass Spectrometry (MIMS) Imaging Applications in Stem Cell Biology.

Multi-isotope imaging mass spectrometry (MIMS) allows the measurement of turnover of molecules within intracellular compartments with a spatial resolution down to 30 nm. We use molecules enriched in stable isotopes administered to animals by diet or injection, or to cells through the culture medium. The stable isotopes used are, in general, 15 N, 13 C, 18 O, and 2 H. For stem cell studies, we essentially use 15 N-thymidine, 13 C-thymidine, and 81 Br from BrdU. This protocol describes the practical use of MIMS with specific reference to applications in stem cell research. This includes choice and administration of stable isotope label(s), sample preparation, best practice for high-resolution imaging, secondary ion mass spectrometry using the Cameca NanoSIMS 50L, and methods for robust statistical analysis of label incorporation in regions of interest (ROI). © 2021 The Authors. Current Protocols published by Wiley Periodicals LLC. Basic Protocol 1: Stable isotope labeling of DNA in cultured cells Basic Protocol 2: Stable isotope labeling of DNA in animals Basic Protocol 3: Preparation of Si chips, the general sample support for NanoSIMS analysis Basic Protocol 4: Stable isotope analysis of DNA replication in single nuclei in a population of cells with NanoSIMS Basic Protocol 5: Data reduction and processing.

(Invited) Conformal Printing for Advanced Electronic Devices

Different electronic devices are ubiquitous in our daily lives. These devices keep on improving daily, and their evolution contributes to the enrichment of our lives. However, two factors remain, that is, little or no progress at all has been introduced in the field of electronics for a long time. First, the use of a printed circuit board (PCB) to drive electronic-device circuits has not been improved. The PCB remains thick and hard. Second, the PCB is enclosed in a cabinet for finished products. Generally, device engineers and product designers design electronic circuits and cabinets, respectively. In this case, engineers emphasize that they cannot change the circuit size and arrangement of the lead-out wiring, whereas designers insist that they must realize an attractive cabinet beyond the restriction of the circuit designs.To overcome this issue, conformal printing using a soft blanket has attracted much attention as a technique that can form wires/electrodes on objects with complex shapes. Although the cabinets of electronic devices often have a curved surface, printing that uses a soft blanket can simply and easily form patterns on these electronic devices. At least, wires/electrodes can be formed on a cabinet with a complex shape. Among the many printing methods, the screen-printing-based technology is the most practical. The wires/electrodes of various commercially available electronic devices are fabricated using this printing method. Thus, we are developing screen-printing-based conformal-printing techniques such as screen-offset and screen-pad printing.Screen-offset printing involves screen printing onto a blanket made of silicone and transfer printing from the blanket to a substrate [Fig. 1(a)]. In this process, the organic solvents in conductive ink are absorbed by the silicone. Therefore, collapse of the patterns due to cohesion failure during transfer printing can be prevented. In addition, solvent absorption prevents ink from smudging caused by its fluidity, which subsequently means that fine patterns can be formed compared with those obtained using the conventional screen printing. The width of the patterns formed by screen-offset printing can be as fine as 10 µm, whereas the minimum width obtained by screen printing in mass-produced products is approximately 40–50 µm.Furthermore, the surface free-energy of silicone is low, indicating that screen-offset printing can form patterns even on an adhesive. For example, a material sticks to a screen mask when conventional screen printing is employed. Although heat-applied soldering is often employed for electronic-component mounting, non-heated interconnection can be performed by fixing the electronic components on a screen-offset-printed adhesive substrate using an alignment of component and substrate electrodes.Another feature of the screen-offset printing is that the silicone blanket can deform along the shape of a substrate owing to its softness, which indicates that the conductive ink can be transcriptionally formed on the surface of an object with a complex shape. For example, we developed printed wire-bonding techniques using screen-offset printing [Fig. 1(b)]. A 200-µm-thick Si chip with face-up-type electrodes was arranged on a PCB. Using screen-offset printing, the conductive-ink patterns could climb over the cleaved sidewall of the Si chip because silicone can deform along the steric structure. Thus, wiring connections between the PCB pads and Si-chip pads were successfully performed.Furthermore, screen-offset printing can properly form conductive patterns on textiles [Fig. 1(c)]. For example, plain-woven cotton, which is often used for clothes such as shirts, has a bumpy and porous surface, implying that forming wires/electrodes without breaking is very difficult. However, the silicone blanket can deform along the textured surface. In addition, dried ink caused by organic-solvent absorption of the blanket can bridge the air gap. This wiring technique can contribute to the e-textile technology as a platform for wearable electronics.Applying screen-offset printing on a surface with a large step on the order of millimeters is difficult. To overcome this problem, we need to employ a much softer and thicker blanket to drastically deform along the substrate surface. In contrast, screen printing ink onto such a softer blanket becomes difficult. To address this issue, we have developed screen-pad printing, which is composed of the following: (i) screen printing to a normal blanket, (ii) picking ink to a soft pad from the blanket, and (iii) transcriptionally forming ink patterns on a substrate from the pad. Patterns can be formed even on bumpy surfaces with a large step owing to the soft pad, although the number of processes increases.Common objects generally do not have a flat surface but have a complicated shape. We are currently attempting to fabricate such object-sensor devices by forming functional-material patterns using our developed conformal-printing technique. Figure 1

(Invited) Thermoelectric Properties of Tin-Incorporated Group-IV Thin Films

Integration of a thin-film energy-harvesting device in a silicon (Si) chip strongly desires to realize a standalone sensing network system called the internet-of-things (IoT) society. The thermoelectric generator (TEG), which could convert waste heat into electricity, is one option. Considering many IoT sensors will be distributed worldwide, it is desirable to manufacture them using the same technology as next-generation Si-based integrated circuits, including the material. Tin-incorporated group-IV materials, such as germanium tin (Ge1−x Sn x ) and silicon tin (Si1−x Sn x ), theoretically possess a lower thermal conductivity [1] than those of Ge and Si, respectively, owing to the mass-difference scattering of phonons. Thermoelectric efficiency is inversely proportional to thermal conductivity; hence, the tin-incorporated group-IV thin films are one of the attractive TEG materials. The low thermal conductivity also helps ensure temperature differences within small TEG devices.Against the background, this paper will discuss the thermoelectric properties of the tin-incorporated group-IV thin films grown by low-temperature molecular beam epitaxy. The thermal conductivity of Ge0.95Sn0.05 was reduced down to 2.5 Wm−1K−1 [2] by introducing the stacking faults due to microscopic tilt in the crystals, which value is 4% of bulk-Ge (60 Wm−1K−1 [3]). The stacking faults did not have much adverse effect on carrier conduction, especially for electron conduction. Additionally, relatively high-power factors of ~10 and ~30 μWcm−1K−2 at room temperature (RT) were realized for the p- and n-type Ge1−x Sn x layers, respectively. The power factor for the n-type layers is comparable with the counterpart of the n-type BiTe-based layers (~25 μWcm−1K−2 at RT) [4]. Combined with the recent progress in the polycrystalline layers [5], we will present a guideline for enhancing the power factor in Sn-incorporated group-IV materials. Acknowledgments This work as partly supported by PRESTO (No. JPMJPR15R2) and CREST (No. JPMJCR19Q5) from the JST in Japan, JSPS KAKENHI (Nos. 19K21971, 19H00853, 20H05188, 21H01366), and a research grant (Creation of Life Innovation Materials for Interdisciplinary and International Researcher Development) from the MEXT in Japan.

Extensive Broadband Near-Infrared Emissions from GexSi1-x Alloys on Micro-Hole Patterned Si(001) Substrates.

Broadband near-infrared (NIR) luminescent materials have been continuously pursued as promising candidates for optoelectronic devices crucial for wide applications in night vision, environment monitoring, biological imaging, etc. Here, graded GexSi1−x (x = 0.1–0.3) alloys are grown on micro-hole patterned Si(001) substrates. Barn-like islands and branch-like nanostructures appear at regions in-between micro-holes and the sidewalls of micro-holes, respectively. The former is driven by the efficient strain relation. The latter is induced by the dislocations originating from defects at sidewalls after etching. An extensive broadband photoluminescence (PL) spectrum is observed in the NIR wavelength range of 1200–2200 nm. Moreover, the integrated intensity of the PL can be enhanced by over six times in comparison with that from the reference sample on a flat substrate. Such an extensively broad and strong PL spectrum is attributed to the coupling between the emissions of GeSi alloys and the guided resonant modes in ordered micro-holes and the strain-enhanced decomposition of alloys during growth on the micro-hole patterned substrate. These results demonstrate that the graded GexSi1−x alloys on micro-hole pattered Si substrates may have great potential for the development of innovative broadband NIR optoelectronic devices, particularly to realize entire systems on a Si chip.

An Array of On-Chip Integrated, Individually Addressable Capacitive Field-Effect Sensors with Control Gate: Design and Modelling.

The on-chip integration of multiple biochemical sensors based on field-effect electrolyte-insulator-semiconductor capacitors (EISCAP) is challenging due to technological difficulties in realization of electrically isolated EISCAPs on the same Si chip. In this work, we present a new simple design for an array of on-chip integrated, individually electrically addressable EISCAPs with an additional control gate (CG-EISCAP). The existence of the CG enables an addressable activation or deactivation of on-chip integrated individual CG-EISCAPs by simple electrical switching the CG of each sensor in various setups, and makes the new design capable for multianalyte detection without cross-talk effects between the sensors in the array. The new designed CG-EISCAP chip was modelled in so-called floating/short-circuited and floating/capacitively-coupled setups, and the corresponding electrical equivalent circuits were developed. In addition, the capacitance-voltage curves of the CG-EISCAP chip in different setups were simulated and compared with that of a single EISCAP sensor. Moreover, the sensitivity of the CG-EISCAP chip to surface potential changes induced by biochemical reactions was simulated and an impact of different parameters, such as gate voltage, insulator thickness and doping concentration in Si, on the sensitivity has been discussed.

Polymer-Based Biocompatible Packaging for Implantable Devices: Packaging Method, Materials, and Reliability Simulation.

Polymer materials attract more and more interests for a biocompatible package of novel implantable medical devices. Medical implants need to be packaged in a biocompatible way to minimize FBR (Foreign Body Reaction) of the implant. One of the most advanced implantable devices is neural prosthesis device, which consists of polymeric neural electrode and silicon neural signal processing integrated circuit (IC). The overall neural interface system should be packaged in a biocompatible way to be implanted in a patient. The biocompatible packaging is being mainly achieved in two approaches; (1) polymer encapsulation of conventional package based on die attach, wire bond, solder bump, etc. (2) chip-level integrated interconnect, which integrates Si chip with metal thin film deposition through sacrificial release technique. The polymer encapsulation must cover different materials, creating a multitude of interface, which is of much importance in long-term reliability of the implanted biocompatible package. Another failure mode is bio-fluid penetration through the polymer encapsulation layer. To prevent bio-fluid leakage, a diffusion barrier is frequently added to the polymer packaging layer. Such a diffusion barrier is also used in polymer-based neural electrodes. This review paper presents the summary of biocompatible packaging techniques, packaging materials focusing on encapsulation polymer materials and diffusion barrier, and a FEM-based modeling and simulation to study the biocompatible package reliability.

A Soft Tactile Sensor Based on Magnetics and Hybrid Flexible-Rigid Electronics.

Tactile sensing is crucial for robots to manipulate objects successfully. However, integrating tactile sensors into robotic hands is still challenging, mainly due to the need to cover small multi-curved surfaces with several components that must be miniaturized. In this paper, we report the design of a novel magnetic-based tactile sensor to be integrated into the robotic hand of the humanoid robot Vizzy. We designed and fabricated a flexible 4 × 2 matrix of Si chips of magnetoresistive spin valve sensors that, coupled with a single small magnet, can measure contact forces from 0.1 to 5 N on multiple locations over the surface of a robotic fingertip; this design is innovative with respect to previous works in the literature, and it is made possible by careful engineering and miniaturization of the custom-made electronic components that we employ. In addition, we characterize the behavior of the sensor through a COMSOL simulation, which can be used to generate optimized designs for sensors with different geometries.

Geometrical Effects on Ultrasonic Al Bump Direct Bonding for Microsystem Integration: Simulation and Experiments.

This study employed finite element analysis to simulate ultrasonic metal bump direct bonding. The stress distribution on bonding interfaces in metal bump arrays made of Al, Cu, and Ni/Pd/Au was simulated by adjusting geometrical parameters of the bumps, including the shape, size, and height; the bonding was performed with ultrasonic vibration with a frequency of 35 kHz under a force of 200 N, temperature of 200 °C, and duration of 5 s. The simulation results revealed that the maximum stress of square bumps was greater than that of round bumps. The maximum stress of little square bumps was at least 15% greater than those of little round bumps and big round bumps. An experimental demonstration was performed in which bumps were created on Si chips through Al sputtering and lithography processes. Subtractive lithography etching was the only effective process for the bonding of bumps, and Ar plasma treatment magnified the joint strength. The actual joint shear strength was positively proportional to the simulated maximum stress. Specifically, the shear strength reached 44.6 MPa in the case of ultrasonic bonding for the little Al square bumps.

Metallization-free silver sinter bonding to silicon via in situ decomposition of silver oxalate

Metallization-free Ag sinter bonding to Si and SiO2 substrates was achieved via the thermal decomposition of Ag oxalate. Ag oxalate generated atomic-scale Ag through decomposition at approximately 200 °C and transformed into sintered Ag. Ag derived from Ag oxalate successfully bonded to Si substrates through close contact formation with Si surface oxide. Similarly, amorphous and α-quartz SiO2 substrates were directly bonded with Ag. These results indicate that the atomic-scale Ag generated on SiO2 contributed to interface formation over a large area. Moreover, the joints of the bare Si chip and metal substrate showed a maximum shear strength of 29 MPa at a bonding temperature of 250 °C and a bonding pressure of 5 MPa. The in-situ generation of Ag through the decomposition of Ag precursors can facilitate the direct bonding of electronic materials, making the proposed method a promising one for electronics applications.

Theoretical and experimental Raman study for mechanical stress in die-attach process

We measured the stress in a Si chip mounted on a Cu plate using Raman spectroscopy and compared the results with those calculated by using the finite element method (FEM). The difference in the stress observed at the vicinity of the chip edge was approximately 30 MPa, and the simulated value was smaller than that observed using Raman spectroscopy. We found that the difference occurred owing to the absence of the “filet” structure generated from the epoxy adhesive, and we subsequently modified the simulation model. The modified FEM results were in good agreement with the measured results. These results indicated that the “filet” structure, which was not the main structure of die-bonding, played an important role in residual stress formation. Feedback using Raman measurements is crucial, and we evaluated the stress in electronic devices with high accuracy by combining FEM with Raman microprobe measurements. In cross-sectional measurements, we observed discrepancy between the results, and the difference in the vertical stress was found to be dependent on excitation laser wavelength. Except for the discrepancy near the backside, the Raman results were in good agreement with the FEM results. This indicated that Raman spectroscopy can evaluate the stress components in the Si cross-section, and full three-dimensional stress in the packaging devices can be determined by combining FEM with cross-sectional Raman measurements, even if the internal stress is relaxed via cutting.