Si-based Transistors Research Articles

Present and Future of Si-Based Transistor Technology for Memories

Nanotechnology is named as a promising research area for the semiconductor technology to be extended or replaced by it. Since the silicon based devices such as NAND Flash memory, DRAM, SRAM, and CPUs are scaled down below 100 nm entering into the nanoscale regime late 1990s, in the middle of 2005, we are already facing the appearance of sub 50 nm technology in production. In this paper, we introduce recent technology development activities in Samsung to realize the sub 50 nm technologies into the devices such as SRAM, DRAM, and Flash memories as well as the high performance logic devices. RCAT (Recessed Cell Array Transistor), PiFET (Partially-insulated MOSFET) and FinFET, McFET (Multi channel FET), MBCFET (Multi- Bridge Channel MOSFET), and Twin Silicon Nanowire MOSFET (TSNWFET) are the 3-dimensional structure CMOS transistors to be introduced for nanoscale applications.

Strained ultrahigh performance fully depleted nMOSFETs with f/sub t/ of 330 GHz and sub-30-nm gate lengths

Ultrahigh performance fully depleted nMOSFETs have been fabricated on ultra-thin silicon-on-insulator (UTSOI) with a body thickness of 18 nm and channel lengths down to 20 nm. Uniaxial tensile stress induced in the channel using stressed contact liners and stress memorization was found to significantly improve ac performance, resulting in cutoff frequencies f/sub t/ as high as 330 GHz. This is the highest f/sub T/ value reported on fully depleted UTSOI MOSFETs and is among the highest f/sub T/ values for any Si-based field-effect transistor. Stress memorization and stressed contact liners were found to have little impact on gate to source capacitance indicating that the enhancement in f/sub T/ results primarily from stress-induced enhancements in transconductance.

The influence of collector dopant profile on breakdown voltage and cutoff frequency of Si‐based RF bipolar transistors

The cutoff frequency ft and the collector-emitter breakdown voltage BVCEO are computed for various types of Si-based bipolar junction transistors with different doping profiles of the selectively implanted collectors (SIC). In particular the influence of the SIC profiles on the ft vs. BVCEO characteristics is investigated. It is shown that for slow BJTs the effects of collector profile variations are negligible. For fast HBTs, however, the actual SIC profile has a significant influence on the ft vs. BVCEO characteristics. Graded and steplike SIC profiles show an improvement compared to constant SIC doping, while retrograde profile deteriorate device performance. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Present and Future of Si-based Transistor Technology for Memories

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A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 × 6 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 252 GHz and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 μA, and a peak dc /spl beta/ of 36 were measured.

AlGaN/GaN HEMTs on Si substrate with 7 W/mm output power density at 10 GHz

The first 10 GHz power performance of AlGaN/GaN HEMTs on silicon substrate is reported. Molecular beam epitaxy grown AlGaN/GaN heterostructure and field-plate gates with 0.3 µm length are employed to fabricate the devices on 2-inch Si (111) substrates. A maximum current density of 850 mA/mm and an extrinsic transconductance of 220 mS/mm are achieved. Load pull measurements at 10 GHz demonstrate a continuous-wave output power density of 7 W/mm, which is the highest power density reported to date for an Si-based transistor. A peak power added efficiency of 52% is achieved for these devices at 10 GHz.

Complementary tunneling transistor for low power application

The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

A doping concentration-dependent upper limit of the breakdown voltage–cutoff frequency product in Si bipolar transistors

Recent high-speed Si-based bipolar transistors apparently exceed the Johnson Limit in terms of breakdown voltage–cutoff frequency product, and this paper addresses the relevant issues. First, BV CES rather than BV CEO is shown to be the representative breakdown voltage in describing the breakdown-speed trade-off in collector design, since BV CEO is modulated by the current gain which is irrelevant of the collector design and also practical bipolar circuits are rarely operated with open-base condition for which BV CEO is defined. In the same context, it is suggested BV CES be employed in representing the upper limit of breakdown voltage–cutoff frequency product. Second, a collector doping concentration-dependent upper limit of BV CES· f T product is proposed incorporating the doping concentration-dependent critical electric field and accurate values for related device parameters. With this new approach, it is shown that the limit is far larger than the Johnson Limit and the limit is still yet to be reached.

Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.

Conducting barriers for vertical integration of ferroelectric capacitors on Si

One of the issues impeding the commercialization of nonvolatile ferroelectric memories is the identification and development of a conducting diffusion barrier for the vertical integration of ferroelectric capacitors on Si-based transistors. We report results on the use of Ti–Al alloys as such a diffusion barrier. Our results indicate that it maintains its structural integrity and electrical conductivity after the deposition of a lead-based ferroelectric stack at 650 °C. The electrical properties of the capacitors were measured through the barrier layer by making direct contact to the diffusion barrier. The properties of the capacitors measured by direct contact to the Ti–Al alloy show clearly the absence of an insulating interfacial layer. Transmission electron microscopy and Rutherford backscattering studies confirm that there is no oxidation of the conducting barrier and no reaction between it and the electrode.

Thermal properties and thermal instabilities of InP-based heterojunction bipolar transistors

We investigate the physical parameters which are critical to the understanding of the thermal phenomena in InP-based heterojunction bipolar transistors. These parameters include thermal resistance, thermal-electric feedback coefficient, current gain, and base-collector leakage current. We examine the thermal instability behavior in multi-finger HBTs, and observe for the first time the collapse of current gain in InP-based HBTs. Based on both measurement and modeling results, we establish the reasons why the collapse is rarely observed in InP HBT's, in a sharp contrast to AlGaAs/GaAs HBT's. We compare the similarities and differences on how InP-based HBT, GaAs-based HBT, and Si-based bipolar transistors react once the thermal instability condition is met. Finally, we describe the issues involved in the design of InP HBTs.

Assessment of SixGe1-x epitaxial alloys grown on silicon at 350°C

Since an established epitaxial materials system for the fabrication of Si-based heterojuaction bipolar transistors (HBTs) does not currently exist, several groups are now evaluating SixGe1-x epitaxial alloys for the base region of a Si HBT. A reduced band gap with the potential for reduced resistance in a SixGe1-x base are the attractive features of this structure. Additionally, there might be other applications for SixGe1-x epitaxial structures in device technology. However, as with any lattice-mismatched heteroepitaxial system, the potential for creation of deleterious threading dislocations exists. Also, the formation of a planar array of misfit dislocations could prove to be detrimental to HBT device performance and/or longevity. Hence, the investigation of various methods of producing SixGe1-x epitaxial films combined with detailed analytical characterization is necessary before a, viable device technology is realized. This contribution reports briefly on SixGe1-x epitaxial films that have been grown on Si(100) at 350 ° C by remote plasma-enhanced chemical vapor deposition (RPECVD).