Short Gate Length Research Articles

(Invited) Oxide Semiconductor Gain Cell Memory

The energy and delay consumed by the off-chip memory (DRAM) and memory-to-logic chip data movement becomes the bottleneck (known as the memory wall) for the computing systems nowadays, especially for abundant-data computing and neural network accelerators. Larger on-chip memory capacity with high bandwidth can be a solution, yet it is difficult to achieve using SRAM and DRAM. Oxide semiconductor FET (OSFET)-based gain cell memory on the logic platform provides higher density than SRAM due to 3D stacking and is an attractive complement to off-chip DRAM. OSFET with extremely low leakage is used as the write transistor for long retention time, while the read transistor can either adopt OSFET for multiple-layer stacking (OS-OS gain cell) or Si FET for higher read speed (Hybrid gain cell). Designing OSFET gain cell is more than simply choosing materials/device designs that have the lowest off-state leakage current for the longest retention time. Atomic Layer Deposition (ALD) Indium Tin Oxide (ITO) FET is chosen to balance retention time with memory bandwidth. With material, process, and device co-design, the ITO films deposited by ALD with TMIn precursor, 9:1 In:Sn cycle ratio, and 2nm thickness exhibited optimized characteristics for OSFET-based gain cell. The experimentally optimized device exhibits low off-current 2×10-18 A/µm, high on-current 26.8 µA/µm, low SS 70 mV/dec, and high mobility 27 cm2/Vs. It also shows good stability with small VTH shift < 0.2 V under 125 °C, low PBS shift < 0.35 V and low NBS shift < 0.1 V under 1000s bias stress. Oxide semiconductor transistors is an accumulation mode transistor that requires a gate electric field to turn off the transistor. The transistor design calls for nanometer-thin oxide semiconductor channels. Significant device design tradeoffs exists between high on-current, low off-current, short gate length scalability, and the setting of proper threshold voltages. This talk will give an overview of the above experimental achievements today and the device design considerations for future gain cell memories.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

Lateral ionic-gated graphene synaptic transistor with transition from paired-pulse facilitation to depression for filtering and image recognition

The transition from paired-pulse facilitation to paired-pulse depression is of significant importance for regulating biologic neural network. Here, we fabricate and investigate a lateral ionic-gated graphene synaptic transistor (GST) with short gate length. We control the channel current via e-field-dependent movement and diffusion of ions for realizing the transition from paired-pulse facilitation to depression. This phenomenon comes from the over-diffusion and trapping of a finite number of ions and the short ion-diffusion length under large negative gate pulse stimuli. This device successfully emulates facilitation and depression synaptic functions, for leveraging the accumulation, migration and diffusion of ions. Moreover, enhanced high-pass filtering and conversion from long-term depression to long-term potentiation are achieved by changing pulses time interval. Our results indicate that our device possesses excellent frequency-dependent synaptic plasticity, making it highly suitable for information filtering up to 33 Hz in neuromorphic systems, and image edge enhancement for neural image processing. In additional, a simulated artificial neural network built on lateral ionic-gated GSTs for handwritten digit recognition can achieve a learning accuracy of 82.4 %.

Investigation of RF performance of Ku-band GaN HEMT device and an in-depth analysis of short channel effects

In this paper, we have characterized an AlGaN/GaN High Electron Mobility Transistor (HEMT) with a short gate length (Lg ≈ 0.15 μm). We have studied the effect of short gate length on the small signal parameters, linearity parameters and gm-gd ratio in GaN HEMT devices. To understand how scaling results in the variation of the above-mentioned parameters a comparative study with higher gate length devices on similar heterostructure is also presented here. We have scaled down the gate length but the barrier thickness(tbar) remained same which affects the aspect ratio (Lg/tbar) of the device and its inseparable consequences are the prominent short channel effects (SCEs) barring the optimum output performance of the device. These interesting phenomena were studied in detail and explored over a temperature range of −40 °C to 80 °C. To the best of our knowledge this paper explores temperature dependence of SCEs of GaN HEMT for the first time. With an approach to reduce the impact of SCEs a simulation study in Silvaco TCAD was carried out and it is observed that a recessed gate structure on conventional heterostructure successfully reduces SCEs and improves RF performance of the device. This work gives an overall view of gate length scaling on conventional AlGaN/GaN HEMTs.

Low-resistive gate module for RF GaN-HFETs by electroplating

This paper presents a novel approach for reducing the gate resistance (R g) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH’s Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μm to approximately 1.0 μm for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency at 20 GHz and V ds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.

Physical insight of thin AlGaN back barrier for millimeter-wave high voltage AlN/GaN on SiC HEMTs

In this work, physical mechanisms underlying carbon-doped buffer combined with an AlGaN back-barrier layer are investigated in state-of-the-art millimeter-wave AlN/GaN transistors. We have fabricated devices with and without the insertion of a thin AlGaN back-barrier layer with reduced carbon concentration to analyze the improvement resulting from this buffer architecture. More specifically, the impact of the Al mole fraction into the back-barrier, carbon doping in the buffer, and channel thickness on 100 nm gate length device performance has been studied. It appears that a 150 nm undoped GaN channel followed by a highly carbon-doped GaN buffer results in good electron confinement at the expense of a high current collapse. On the other hand, an Al mole fraction of 25% in the AlGaN back barrier layer coupled with a 150 nm undoped GaN channel provides excellent electron confinement, resulting not only in a low DIBL under high electric field but also low current collapse. Calibrated on experimental devices, TCAD simulations reveal that the electric field penetration inside the GaN buffer is prevented owing to a strong polarization from the back barrier when the Al-content is high enough. That is why, the electron confinement is superior for the 25% Al mole fraction in the back barrier along with reduced current collapse. As a result, careful engineering of the carbon concentration together with the undoped GaN channel thickness is crucial to achieve robust devices, which can, thus, deliver high device performance with superior voltage operation while using short gate lengths.

Analytical modeling of negative capacitance transistor based ultra low power Schmitt trigger

Through an analytical framework, the work showcases the potential benefits of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) negative capacitance (NC) transistor (T) to enhance the hysteresis width (ΔVH) and reduce the minimum supply voltage (Vdd,min) of ultra low power (ULP) subthreshold Schmitt trigger (ST) at shorter gate lengths. Analyzing different ST configurations i.e. 2T (both NCFET), 4T-hybrid (realized through combination of NCFETs and MOSFETs), and 6T (all NCFETs or MOSFETs), leads to the inferences that (i) an inherent negative differential resistance of NCFET can be utilized for hysteresis in 2T-ST circuit, (ii) 4T-hybrid ST is not beneficial for enhancing ΔVH due to a current mismatch between MOSFET and NCFET, and (iii) an optimized 2T-ST and 6T-ST designed with high-permittivity (κ) sidewall spacer (Si3N4) and ferroelectric layer (6 nm) can function at Vdd,min of ∼ 55 mV, and ∼ 39 mV, respectively. Results indicate towards potential benefits of realizing ULP subthreshold ST through MFMIS NCFETs without any circuit overhead.

Study on the effect of 65 nm NMOS transistor using SILVACO TCAD

This work aims to study the effect of the short gate length of 65 nm NMOS transistor using SILVACO TCAD. A 65 nm NMOS was designed and virtually fabricated and characterized using the ATHENA and ATLAS process and device simulators, respectively. A shorter gate length is expected to experience short channel effects (SCE) such as channel length modulation and drain induced barrier lowering (DIBL). The SCE was observed from the comparison of the long gate length (0.3 µm) and short gate length (65 nm) NMOS transistors’ performances. The result observed from the ID-VD graph showed that the 65 nm NMOS experienced the channel length modulation where the drain current, ID did not saturate as VD increased with an increment of 1.45 at VD = 3.3 V. Several improvements were done to overcome the SCE which are retrograde well implantation and Halo implantation. A 5 × 1014 cm−3 Boron of 200 keV implant energy and a 5 × 1013 cm−3 Boron of 100 keV implant energy were implanted for the retrograde well implant which was shown to reduce the channel length modulation effect. In addition, from the ID-VG graph, the drain current for the 65 nm NMOS was not zero when VG = 0 V, which indicated the DIBL effect. The phosphorus of 2 × 1012 cm−3 and 1 × 1013 cm−3 concentration was implanted for the Halo implantation. The results showed that the inclusion of Halo implantation has reduced the DIBL effect as the ID-VG plot showed that ID = 0 when VD = 0 with the threshold voltage, VTH = 1.87 V respectively. This shows that the inclusion of retrograde well implant and Halo implantation reduces the channel length modulation as well as DIBL effect of the short gate length NMOS.

Impact of undoped channel thickness and carbon concentration on AlN/GaN-on-SiC HEMT performances

We report on a vertically scaled AlN/GaN high electron mobility transistor technology design optimization for millimeter-wave applications. The undoped GaN channel thickness and carbon concentration into the buffer are extensively varied and systematically characterized. It is found that a thin GaN channel, typically below 150 nm improves the electron confinement, but increases the trapping effects, especially when using shorter gate lengths. Moreover, high carbon concentration into the buffer enables not only high electron confinement but also low leakage current under a high electric field at the expense of trapping effects. As a result, the optimum epi-design enabled state-of-the-art RF performances at 40 GHz.

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

This study aims to understand the performance of continuous-wave laser lateral crystallization (CLC) poly-Si1-xGex TFTs. The transfer characteristics of n-ch CLC poly-Si1-xGex TFTs revealed that the threshold voltages shifted in the positive direction compared with those of CLC poly-Si TFTs with increasing Ge concentration. The characteristics of CLC n-ch poly-Si1-xGex TFTs can be explained by the formation of acceptors. For p-ch TFTs, the transfer characteristics of CLC poly-Si1-xGex TFTs exhibited a larger Ioff than those of CLC poly-Si TFTs. The Ion/Ioff ratio is small for p-ch parallel CLC poly-Si1-xGex TFTs and is weakly dependent on the gate length. In contrast, p-ch perpendicular CLC poly-Si1-xGex TFTs exhibit large Ion/Ioff values for long gate lengths. The variation in the Ion/Ioff ratio of p-ch CLC poly-Si1-xGex TFTs according to the parallel or perpendicular and long or short gate length is explained by Ge segregation along the grain boundary, resulting in the formation of a high-concentration p-type conduction region along the grain boundary, which connects the SD regions.

Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions.

Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET

AbstractNegative capacitance field effect transistors is found to be a promising option for low power VLSI devices in the advanced technology node. In this article, through extensive numerical simulation, we report the scaling effect of ferroelectric gate stack, channel thickness and gate length on electrostatic integrity, DC, analog and RF performance of InGaAs quantum well MOS transistor. The different DC and analog figure of merits such as on current (), switching ratio (), threshold voltage roll‐off, sub‐threshold swing (SS), trans‐conductance (), transconductance efficiency () of the test device has been analyzed for different ferroelectric layer thicknesses and compared with the baseline device. We have investigated RF performance such as gate capacitance, unity‐gain cut‐off frequency and small signal voltage gain of the device. Improvement in DC and analog figure of merits is proportional to the ferroelectric layer thickness. However, for higher values of ferroelectric thickness, the hysteresis effect gradually became prominent. MOS transistor with optimum ferroelectric layer thickness shows the negligible amount of threshold voltage roll‐off and improved transconductance‐frequency product compared to the baseline device. In presence of ferroelectric layer, the effect of channel thickness variation on device performance is reduced. The role of ferroelectric gate stack is found to be more prominent at shorter gate length.

A Ballistic Transport Nanodevice Based on Graphene Nanoribbon FET by Enhanced Productivity for Both Low-Voltage and Radio-Frequency Scopes

The top performance in both the low-voltage and radio frequency (RF) scopes has been nominated for an unique nanodevice made from a graphene nanoribbon with an extremely short gate length (7.5 nm) in this study. Two distinct material engineering options were used, yielding some interesting outcomes. Due to the use of an ultrascale GNRFET in this study, the band structure non-linearity in the Dirac point and the energy-position dependent effective mass model for dual material gate architectures were examined for the first time. The NEGF formalism is used to carry out both the low-voltage and RF research using a three-dimensional (3D) Poisson equation. Low-voltage high performance has been validated by monitoring the key parameters in the terms of on current (Ion), off current (Ioff), Ion to Ioff ratio, subthreshold swing, and drain induced barrier lowering (DIBL) for the proposed device as compared to other structures under the study. The RF performance is examined by evaluation of essential parameters in the cases of parasitic gate capacitance, intrinsic cut-off frequency, intrinsic delay time, and transconductance. Indeed, a device with a higher source side gate work function than it does on the drain side is proposed will shift the energy band from the device’s half to the drain electrode, altering carrier outflow. In addition, the performance of non-linearity and RF intermodulation distortion has been analyzed for all devices under investigation in order to attain the best attitude toward the suggested device in comparison to the other devices under investigation in this work.

AlGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

In this work, an AlGaN/GaN HEMT structure is grown on a 0.8 μm thick 3C-SiC layer on high resistivity Silicon substrate. The RF propagation losses are investigated and compared with the ones of epi-layers grown directly on Silicon and on 6H-SiC substrates. Short gate length transistors are fabricated using e-beam lithography. In spite of ohmic contact resistance of 0.6 Ω.mm, a saturated current density of 0.7 A/mm at a gate bias of +1V and a transconductance peak higher to 250 mS/mm for 75 nm T-shaped gate transistors are reached on structure with thick 3C-SiC template. Moreover, for the first time, transition frequencies fT/fmax of 60/98 GHz are reported on such 3C-SiC template.

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters.

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15–22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.

Marine predators algorithm for performance optimization of nanoscale FinFET

Fin-shaped Field Effect Transistors (FinFETs) have proved to be an effective solution when transistors are downscaled and conventional MOSFETs do not perform appreciably well in nanoscale regime. The current work emphasizes on the optimization of Rectzoidal FinFET design at shorter gate length and evaluates short channel effects for 20 nm gate length. Various device dimensions like fin width, fin height, equivalent gate oxide thickness, gate material work-function decide the device performance which is, in fact, measured by leakage current, on-current and short channel effects such as Subthreshold swing. Design and simulations for device have been executed in TCAD tool. After simulations, the performance of designed FinFET structure is optimized with the use of marine predators algorithm (MPA), which is an effective optimization technique inspired from foraging strategy opted by ocean predators. A dataset of fin height and fin width acts as input to artificial neural network, which outputs a trained network. Trained network along with the fitness function is inputted to MPA, and optimized output when verified with TCAD results, produces acceptable results. Fitness function tends to reduce the short channel effects and enhance on-current of device. Approximate optimized fin width and fin height values of designed FinFET are 5 nm and 24 nm respectively. This optimized miniaturized device design is appropriate for transistors which are further employed in numerous nanoscale applications.

Effects of gate length on GaN HEMT performance at room temperature

We report the electrical characteristics at room temperature of (Al,Ga)N/GaN high-electron-mobility transistors with different gate lengths Lg ranging from 0.15 to 2 μm. Static measurements demonstrate an increase of leakage current, whereas the maximum drain–source current and maximum transconductance decrease with increase of the gate length. In addition, drain current–voltage measurements for gate voltage Vgs = −3 V reveal a kink effect, which is pronounced for Lg = 0.15, 0.25, and 0.5 μm and is absent for Lg = 1 and 2 μm. Furthermore, a self-heating effect on the drain current is observed at Vgs = 0 V for a short gate length. By means of deep level transient spectroscopy, we detected one hole trap H1, which is considered to be the main cause of the observed kink effect. Also, the effect of gate length on the static output characteristics and the deep level transient spectroscopy results for Al0.25Ga0.75N/GaN high-electron-mobility transistors is also discussed.

Electrical and thermal analysis of AlGaN/GaN HEMTs transferred onto diamond substrate through an aluminum nitride layer

AbstractIn this paper, electrical and thermal analysis of short gate length AlGaN/GaN HEMTs (high electron mobility transistors) transferred onto diamond substrate through aluminum nitride (AlN) layer are provided. The specific transfer technology uses sputtered AlN as bonding layer. An improvement in maximum DC current density of 14% is observed after transfer on the diamond substrate, with attractive RF performances as well. Lag effects are evaluated thanks to pulsed measurement. Thermal analysis is also proposed to quantify the effects of bonding on self‐heating. Both electrical and thermal characterizations are used as markers to evaluate the impact of the transfer process on the developed HEMT.

Sub-10-nm Scalability of Emerging Nanowire Junctionless FETs Using a Schottky Metallic Core

Inefficient volume depletion is a dominant leakage mechanism in junctionless (JL) field-effect transistors (FET). Moreover, the realization of efficient volume depletion is compensated by the detrimental leakage mechanism of the lateral band-to-band tunneling (L-BTBT), which drastically degrades the performance of nanowire (NW) JLFETs with short gate lengths. A Schottky metallic core (SC) nanowire (NW) junctionless (JL) FET is therefore proposed herein to realize efficient volume depletion along with a significant reduction of the L-BTBT-induced parasitic leakage. Using calibrated three-dimensional (3-D) simulations, it is demonstrated that the presence of a Schottky metallic core effectively depletes the surrounding NW shell by abolishing the shielding effect of holes, which helps in realizing the efficient volume depletion that is desirable in OFF-state. Furthermore, it also leads to a significant reduction of the L-BTBT-induced parasitic bipolar junction transistor (BJT) action. This simultaneous suppression of both leakage mechanisms reduces the OFF-state current by around eight orders of magnitude, leading to a significant ON-state to OFF-state current (ION/IOFF) ratio of ~ 109 for a gate length of 20 nm. The reduced parasitic BJT action facilitates the scaling of SC NW JLFET, leading to a remarkable ION/IOFF ratio of ~ 107 even at a scaled gate length of 7 nm. The Schottky junction results in a vertical electric field that hinders the lateral electrostatic coupling of the drain field lines with the channel, leading to reduced detrimental short-channel effects in the sub-10-nm regime. This immunity against short-channel effects is further boosted by using high-k spacers. Thus, the excellent OFF-state behavior along with the reduced short-channel effects provides an incentive for realizing the proposed SC NW JLFET at sub-10-nm technology nodes.

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

In this report, we study nonlinear electrical behaviors found in vertical-architecture transistors based on wrap-around-gated gallium nitride (GaN) nanowires (NWs) by extending a one-dimensional case of the Landauer-Buttiker formula. Here, the GaN NWs are considered “almost” one-dimensional ideal wires connecting the drain and source terminals, with the gate terminal serving to control the flowing current. Unlike previous models, which require several parameters and complex calculations, our proposed model only needs three parameters and simple calculations to match the experimental data. With this model, we confirm that the maximum current before saturation is a consequence of quasi-ballistic drain current. Thus, electron mobility has no effect in this device. Using a simple formulation, we discuss gating hysteresis in the device that is mediated by the selected oxide layer interface. We show that the memory effect of the device is attributed to time-delay current. The shorter gate length increases the transmission coefficient. As a result, the model can be employed to predict the next-generation NW transistor performance.