Short-circuit Withstand Time Research Articles

Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs

The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (TSCWT), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan.

Investigation of the Short-Circuit Withstand Time and On-Resistance Trade-Off of 1.2 kV 4H-SiC Power MOSFETs

The short-circuit withstand time and on-resistance trade-off is investigated in 4H-SiC Power MOSFETs. We compare the static and short circuit withstand time results along with JFET width dependency and PWELL doping variation of MOSFET. We present that smaller Rds,on by wider JFET width and lighter doped PWELL results in worse short circuit withstand time.

A novel SiC VD-MOSFET with optimized P-type shielding structure in JFET region for improved short circuit robustness

This paper investigates the short-circuit characteristics of Silicon Carbide (SiC) Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistor (VD-MOSFET) utilizing TCAD tools. Expanding upon the conventional VD-MOSFET structure, a novel 900 V SiC VD-MOSFET with two P-type shielding layers introduced in JFET region (PW-MOSFET), is proposed and designed. In contrast to the traditional VD-MOSFET, PW-MOSFET not only significantly improves short-circuit (SC) reliability but also optimizes static performance. Simulation results reveal that PW-MOSFET demonstrates notably superior SC performance at a DC link voltage of 600 V compared to the traditional VDMOSFET, with a 63% increase in Short-Circuit Withstand Time (SCWT) and a 25% enhancement in Baliga Figure of Merit (FOM). The key factor contributing to this performance enhancement is attributed to the advantageous role of the P-type shielding layers, facilitating adjustments in the current flow path, thereby suppressing saturation current and enhancing the reliability of short-circuit events. Furthermore, the issue of increased characteristic on-state resistance (Ron,sp) resulting from the introduction of the P-type shielding layers is addressed by augmenting the doping concentration in the JFET region.

Investigations of SiC lateral MOSFET with high-k and equivalent variable lateral doping techniques

In this article, a novel high-k and equivalent variable lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and calibrated by numerical simulation. The three-dimensional equivalently P-top region is employed in the drift region, and only one additional ion implantation step is needed to achieve variable lateral doping (VLD) technique. The VLD technique combined with the high-k dielectric in the drift region, not only increases the doping concentration of N-drift region, but also optimizes the electric field distribution in the drift region. Simulation results indicates that the BV, specific on-resistance and the short-circuit withstand time of the proposed Hk VLD LDMOS are improved by 48.91%, 53.6% and 60.2% respectively, compared with those of the conventional LDMOS device.

A Behavior Model of SiC DMOSFET Considering Thermal-Runaway Failures in Short-Circuit and Avalanche Breakdown Faults

Accurate fault simulation and failure prediction have long been challenges for SiC MOSFETs users. This paper presents a behavior model of Silicon Carbide (SiC) double-implanted MOSFET (DMOSFET), considering thermal-runaway failures in short-circuit and avalanche breakdown faults on the basis of cell-level physical processes. The proposed model can simulate the faults with extremely high accuracy and precisely predict SiC DMOSFET’s short-circuit withstand time and critical avalanche energy. By finite-element simulations, cell-level physical processes of short-circuit and avalanche breakdown faults are clarified. The mechanisms of thermal-runaway failures are deeply discussed with references to existing studies. Based on semiconductor and device physics mechanisms, the proposed model is constructed upon a traditional behavior model of SiC MOSFET with several parallel branches that are proposed to describe the thermal-runaway failures during both faults. The Cauer thermal network model is used for estimating junction temperature within it. The proposed model is constructed in Simulink, and it is validated using short-circuit and unclamped inductive switching (UIS) tests.

Influence of JFET Width on Short-Circuit Robustness of 1200 V SiC Power MOSFETs

This paper investigates and compares the static performance and short-circuit (SC) robustness of 1200 V SiC MOSFETs with varying JFET widths (WJFET = 2.0–5.0 μm). Short-circuit measurements as well as electrical-thermal simulations are used to identify thermal distribution and maximum electrical field, providing valuable insights into the design limits. The devices under test (DUTs) with narrow and wide WJFET exhibit different failure mechanisms under SC stress. After the short-circuit failure, interlayer dielectric (ILD) cracks are observed in DUTs with narrow JFET width (WJFET < 3 μm). In contrast, it is discovered that the burn mark is located in the channel region of the device with a wide JFET width. Moreover, the short-circuit withstand time (SCWT) of DUTs with narrow and wide WJFET exhibits varying trends under high temperature conditions (100 °C). These results can help verify the different failure mechanisms and determine an optimal JFET design to improve the trade-off between the static performance and SC ruggedness of the SiC MOSFETs.

A Novel Super-Junction DT-MOS with Floating p Regions to Improve Short-Circuit Ruggedness.

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (tsc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (Ron,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Qgd) and gate-drain capacitance (Cgd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process.

Modelling SiC MOSFET module threshold voltage (VTH) and impact of parallel device ΔVTH on short circuit robustness

In SiC modules, where several power MOSFETs are connected in parallel for high current conduction capability, the issue of threshold voltage (VTH) variation between individual devices can become problematic. In instances where the standard deviation of device VTH is minimized by appropriate VTH pre-screening, non-uniform VTH shift under bias-temperature-instability can lead to increased VTH dispersion and potentially poor current sharing. Although non-destructive for normal operation, VTH dispersion in surge events like short circuits can cause premature module failure. In this paper, experimental investigations backed by theoretical models have been developed to explain the relationship between device VTH dispersion and module VTH shift. This is done for Si and SiC MOSFETs. Five Si/SiC MOSFETs are paralleled in a custom printed-circuit-board allowing individual VTH and module VTH measurements. It is shown that the module VTH is typically between the smallest VTH and the mean VTH, depending on the VTH standard deviation. Using empirical models for MOSFETs in weak inversion derived from the measured subthreshold gate transfer characteristics, the model can estimate module VTH from a dispersion of individual MOSFET VTH. It can also predict the impact of non-uniform VTH shift between constituent devices on the overall module VTH. Finally, the impact of VTH mismatch on current sharing during short circuits in parallel connected SiC MOSFETs is presented. The results show that VTH mismatch in parallel connected SiC MOSFETs reduces the short circuit withstand time from 5 μs to 4.5 μs compared to VTH matched SiC MOSFETs.

Comparison of Gamma Irradiation Effects on Short Circuit Characteristics of SiC MOSFET Power Devices between Planar and Trench Structures

The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation.

SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability

A novel silicon carbide (SiC) trench metal–oxide–semiconductor field-effect transistor (MOSFET) with a dual shield gate (DSG) and optimized junction field-effect transistor (JFET) layer (ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device’s dynamic performance but also greatly enhances the safe operating area (SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET (Con-ATMOS), the specific on-resistance (R on,sp) is significantly reduced at almost the same avalanche breakdown voltage (BV av). Moreover, the DSG structure brings about much smaller reverse transfer capacitance (C rss) and input capacitance (C iss), which helps to reduce the gate–drain charge (Q gd) and gate charge (Q g). Therefore, the high frequency figure of merit (HFFOM) of R on,sp ⋅ Q gd and R on,sp ⋅ Q g for the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively. The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current (I d,sat) at a gate voltage (V gs) of 15 V for the ODSG-TMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate (SG) at a large drain voltage. With the reduced I d,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.

Improved Gate-Voltage-Driven Desaturation Short-Circuit Protection Circuit With Robust Switching Noise Immunity for WBG Power Semiconductors

Wide bandgap (WBG) power semiconductors are used in numerous power conversion applications because of their excellent switching characteristics. However, it is difficult to ensure short-circuit protection for WBG power semiconductors because of their shorter short-circuit withstand time. The fast-switching characteristics of WBG power semiconductors induces severe fluctuations in the drain-source voltage and drain current in switching transients, which results in the false triggering of the protection circuit. Therefore, the fast response speed and switching noise suppression are key requirements of the protection circuit for a WBG power semiconductor. To meet these requirements, an improved gate-voltage-driven desaturation protection circuit with a fast response speed and robust noise immunity is proposed in this study. The effect of switching noise on the proposed protection circuit is analyzed, and a detailed design procedure based on the analysis results is provided. The experimental results indicate that the protection delay of the proposed circuit is within 91 ns; additionally, the proposed circuit can survive switching noise during normal operation. Finally, the noise immunity analysis results are verified through experiments under various protection circuit parameter sets.

Optimized 750V SiC MOSFETs for Electric Vehicle Inverter Operation

We report an AEC-Q101-qualified 750V, 15 mΩ planar SiC MOSFETs with a long short circuit withstand time (SCWT) of > 9μs at VDS=400V and VGS=15V and a low specific on-resistance (RON,SP) of 2.1 mΩ.cm2 at VGS=15V designed for xEV traction inverter applications. The RDS(on) at VGS=15V increases from 15mΩ at 25 °C to 21 mΩ at 175 °C. A low turn-on (EON) and turn-off (EOFF) switching energy loss of 95.5μJ and 67μJ at IDS=75A, VDS=400V was measured at 25 °C. The gate oxide lifetime at worst case operating fields of 5MV/cm is >> 20 years.

Review of Short-circuit Protection Circuits for SiC MOSFETs

Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are commonly used in the power transistor industry owing to their superior conductivity, low switching loss, high-frequency operation, and desirable thermal characteristics. However, the short-circuit withstand time of SiC MOSFETs is shorter than that of Si devices, which is disadvantageous in fault states. Gate drivers for SiC MOSFETs require short-circuit protection and soft termination circuits to detect short circuits and protect the power devices and systems from a short-circuit state. Thus, short-circuit protection circuits for SiC MOSFETs are reviewed in this paper. Accordingly, short-circuit detection circuits classified according to gate-source voltage (VGS), drain-source voltage (VDS), and drain-source current (IDS) detection methods are discussed. Moreover, the merits and demerits of soft termination circuits are reviewed.

Ultrafast Protection of Discrete SiC MOSFETs With PCB Coil-Based Current Sensors

Silicon carbide (SiC) <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s offer significant advantages in terms of improved efficiency and reduced size of power electronic converters. However, they possess lesser short-circuit withstand time than silicon devices. An ultrafast short-circuit protection scheme for TO-247 packaged SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is presented in this article. The protection scheme utilizes printed circuit board (PCB) coils to sense the rate of change of current through SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in a half-bridge circuit. The PCB coils are fabricated near a single interconnect trace between the power device and the dc busbar. To ensure minimal intrusion inside the power-loop, the methodology of selecting the minimum trace length for a desired mutual inductance between the coil and the interconnect trace is presented through finite-element analysis. Experimental results for an SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> subjected to a hard switched fault and a fault under load are presented, and the protection circuit response time under 25 ns is reported. Lastly, the peak current-mode control of a buck converter is implemented using the designed PCB coil-based sensor as current feedback sensor. Therefore, the PCB coil is demonstrated to be an effective alternative for Hall effect and magnetic core-based sensors in current control applications with dc/dc converters.

Study of Vertical Ga2O3 FinFET Short Circuit Ruggedness using Robust TCAD Simulation

In this paper, the short circuit ruggedness of Gallium Oxide (Ga2O3) vertical FinFET is studied using Technology Computer-Aided-Design (TCAD) simulations. Ga2O3 is an emerging ultra-wide bandgap material and Ga2O3 vertical FinFET can achieve the normally-off operation for high voltage applications. Ga2O3 has a relatively low thermal conductivity and, thus, it is critical to explore the design space of Ga2O3 vertical FinFETs to achieve an acceptable short-circuit capability for power applications. In this study, appropriate TCAD models and parameters calibrated to experimental data are used. For the first time, the breakdown voltage simulation accuracy of Ga2O3 vertical FinFETs is studied systematically. It is found that a background carrier generation rate between 105 cm−3s−1 and 1012 cm−3s−1 is required in simulation to obtain correct results. The calibrated and robust setup is then used to study the short circuit withstand time (SCWT) of an 800 V-rated Ga2O3 vertical FinFET with different inter-fin architectures. It is found that, due to the high thermal resistance in Ga2O3, to achieve an SCWT >1 μs, low gate overdrive is needed which increases Ron,sp by 66% and that Ga2O3 might melt before the occurrence of thermal runaway. These results provide important guidance for developing rugged Ga2O3 power transistors.

Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

A novel dual injection enhanced planar gate insulated gate bipolar transistor (IGBT) with self-adaptive hole path (DIE-PIGBT) is proposed. A floating-P region is applied behind the emitter-connected deep trench in z direction and contacted with the N-type carrier stored (N-CS) layer for the proposed IGBT. Compared to the conventional trench shielded planar gate IGBT (CTS-PIGBT), the proposed device further alleviates the negative impact of the N-CS layer on the breakdown voltage (BV) and reduces both the on-state voltage drop (V ceon) and saturated collector current density (J sat). Simulation results show that with the same device thickness of 400 μm, the BV are 4625 V and 4275 V for the proposed and conventional device, respectively. The V ceon at 75 A cm−2 is 2.51 V for the proposed DIE-PIGBT, which is 1.13 V lower than that of the CTS-PIGBT. Furthermore, with similar BV to the conventional one, the device thickness can be reduced to 355 μm for the DIE-PIGBT. Pro. The total gate charge (Q G) and miller plateau charge (Q GC) for the proposed device are reduced by 61.0% and 89.9%, respectively. As a result, the proposed structure has better trade-off relationship between the V ceon and turn-off loss (E off). At the same V ceon of 2.51 V, the E off for the DIE-PIGBT and DIE-PIGBT. Pro are 45.17 mJ cm−2 and 41.01 mJ cm−2, which is reduced by 44.0% and 49.1% when compared to 80.61 mJ cm−2 of the CTS-PIGBT, respectively. Moreover, the J sat is reduced from 619 A cm−2 for the CTS-PIGBT to 368 A cm−2 for the DIE-PIGBT under the V ge of 15 V. The short-circuit withstand time of the DIE-PIGBT is 1.9 times larger than that of the conventional device.

1200-V SiC MOSFET Short-Circuit Ruggedness Evaluation and Methods to Improve Withstand Time

This article presents the short-circuit (SC) capability evaluation of TO-247-3 packaged silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) based on tests under different drain biases and gate biases. Compared with the 900-V Si super-junction MOSFET and the 1200-V Si trench-gate field-stop insulated gate bipolar transistor (IGBT), SiC devices show higher saturation current per die area, which requires more rigorous chip design consideration to reach an acceptable SC withstand time (SCWT). The test results also reveal that the SC withstand capability of SiC MOSFETs can still be enhanced. Thus, in both chip design and detection circuits, several novel approaches investigated in recent years, which could potentially improve SC ruggedness of SiC device-based systems, are discussed at the end of this article.

Benchmarking the robustness of Si and SiC MOSFETs: Unclamped inductive switching and short-circuit performance

The reliability and robustness of power devices are key areas of research for increasing the adoption of wide bandgap power semiconductors. This paper benchmarks the robustness under short-circuit (SC) and unclamped inductive switching (UIS) of 650 V SiC trench MOSFETs, SiC planar MOSFETs and silicon super-junction MOSFETs. The performance is characterised at 75 °C and 150 °C and the results show that the SiC MOSFETs have reduced temperature sensitivity under both SC and UIS conditions, which will be beneficial from the application point of view. In the case of the silicon MOSFET, increasing the temperature enhances the short-circuit withstand time as the peak short-circuit current is reduced. The opposite trend is observed for UIS, with a reduction of robustness as the temperature is increased. The absolute SC and avalanche energies are lower for the SiC MOSFETs, but if the chip areas are considered, the energy densities are higher in the SiC MOSFETs, with the SiC Trench having a superior critical SC energy and the SiC planar having a higher avalanche energy density. The higher critical SC and UIS energy densities in SiC MOSFETs, together with their higher thermal resistances result in higher peak junction temperatures and clear hotspots are identified using Finite Element simulations.

Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design

The commercial success of silicon carbide (SiC) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV, for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a P+ substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to 10 μs, has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by 39%. Two retrograde p-well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of 5×1016 cm-3, with this increasing to a peak value of 2×1018 cm-3, in a 700 nm region beneath the channel.

A 1200 V SiC Trench MOSFET with a Laterally Widened P-Shield Region to Enhance the Short-Circuit Ruggedness

In this paper, a novel 1200 V SiC trench MOSFET with a laterally widened P-shield region (LW-MOSFET) is presented by using the two-dimensional numerical simulation. Compared with the conventional trench MOSFET (CT-MOSFET), the LW-MOSFET demonstrates an effective enhancement on the short-circuit (SC) reliability and the optimization of static performance simultaneously. According to the simulation results, the SC withstand time (SCWT) of the LW-MOSFET at 600 V DC bus voltage can reach 8 μs, while that of the CT-MOSFET is only 3 μs at the same conditions. The main reason is that the laterally widened P-shield region can help to suppress the saturation current and mitigate the huge current accumulation near the trench area, leading to an enhancement of the SC reliability. Moreover, the Baliga’s FOM of the proposed structure is improved by 45.7%, which benefits from the higher breakdown voltage (BV) and the lower specific on-state resistance (Ron, sp) by using the optimized structure. The advantage of static performance is related to the local charge balance behavior provided by the laterally widened P-shield region, which helps to use a higher doped current spread layer (CSL) without bringing a degeneration of BV.