Dual injection enhanced planar gate IGBT with self-adaptive hole path for better trade-off and higher SOA capability

Abstract

A novel dual injection enhanced planar gate insulated gate bipolar transistor (IGBT) with self-adaptive hole path (DIE-PIGBT) is proposed. A floating-P region is applied behind the emitter-connected deep trench in z direction and contacted with the N-type carrier stored (N-CS) layer for the proposed IGBT. Compared to the conventional trench shielded planar gate IGBT (CTS-PIGBT), the proposed device further alleviates the negative impact of the N-CS layer on the breakdown voltage (BV) and reduces both the on-state voltage drop (V ceon) and saturated collector current density (J sat). Simulation results show that with the same device thickness of 400 μm, the BV are 4625 V and 4275 V for the proposed and conventional device, respectively. The V ceon at 75 A cm−2 is 2.51 V for the proposed DIE-PIGBT, which is 1.13 V lower than that of the CTS-PIGBT. Furthermore, with similar BV to the conventional one, the device thickness can be reduced to 355 μm for the DIE-PIGBT. Pro. The total gate charge (Q G) and miller plateau charge (Q GC) for the proposed device are reduced by 61.0% and 89.9%, respectively. As a result, the proposed structure has better trade-off relationship between the V ceon and turn-off loss (E off). At the same V ceon of 2.51 V, the E off for the DIE-PIGBT and DIE-PIGBT. Pro are 45.17 mJ cm−2 and 41.01 mJ cm−2, which is reduced by 44.0% and 49.1% when compared to 80.61 mJ cm−2 of the CTS-PIGBT, respectively. Moreover, the J sat is reduced from 619 A cm−2 for the CTS-PIGBT to 368 A cm−2 for the DIE-PIGBT under the V ge of 15 V. The short-circuit withstand time of the DIE-PIGBT is 1.9 times larger than that of the conventional device.