Short-channel Transistors Research Articles

RF Linearity Performance Potential of Short-Channel Graphene Field-Effect Transistors

The radio-frequency (RF) linearity performance potential of short-channel graphene field-effect transistors (GFETs) is assessed by using a nonlinear small-signal circuit model under the first approximation of ballistic transport. An intrinsic GFET is examined to reveal the key features of GFET linearity, and extrinsic parasitics are then included to assess the overall RF linearity. It is shown that short-channel GFETs can be expected to have a signature behavior versus gate bias that includes a constant-linearity region at low gate bias, sweet spots of high linearity before and after the gate bias for peak cutoff frequency, and poor linearity at the gate bias corresponding to the peak cutoff frequency. It is otherwise found that a GFET offers overall linearity that is comparable to a MOSFET and a CNFET, with the exception that the amount of intermodulation distortion in a GFET is dominated by the drain-injected carriers, a unique outcome of graphene's lack of a bandgap. Qualitative agreement with experiment in the signature behavior of GFET linearity supports the approach and conclusions.

Radiation-Induced Short Channel (RISCE) and Narrow Channel (RINCE) Effects in 65 and 130 nm MOSFETs

The behavior of transistors in commercial-grade complementary metal-oxide semiconductor technologies in the 65 and 130 nm nodes has been explored up to a total ionizing dose of 1 Grad. The large dose tolerance of the thin gate oxide is confirmed, but defects in the spacer and STI oxides have a strong effect on the performance of the transistors. A radiation-induced short channel effect is traced to charge trapping in the spacers used for drain engineering, while a radiation-induced narrow channel effect is due to defect generation in the lateral isolation oxide (STI). These strongly degrade the electrical characteristics of short and narrow channel transistors at high doses, and their magnitude depends on the applied bias and temperature during irradiation in a complex way.

Properties of Self-Aligned Short-Channel Graphene Field-Effect Transistors Based on Boron-Nitride-Dielectric Encapsulation and Edge Contacts

We present the characterization of ballistic graphene field-effect transistors (GFETs) with an effective oxide thickness of 3.5 nm. Graphene channels are fully encapsulated within hexagonal boron nitride, and self-aligned contacts are formed to the edge of the single-layer graphene. Devices of channel lengths (LG) down to 67 nm are fabricated, and a virtual-source transport model is used to model the resulting current-voltage characteristics. The mobility and source-injection velocity as a function of LG yields a mean-free-path, ballistic velocity, and effective mobility of 850 nm, 9.3×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cm/s, and 13700 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, respectively, which are among the highest velocities and mobilities reported for GFETs. Despite these bestin-class attributes, these devices achieve transconductance (gm) and output conductance (gds) of only 600 and 300 μS/μm, respectively, due to the fundamental limitations of graphene's quantum capacitance and zero-bandgap. gm values, which are less than those of comparable ballistic silicon devices, benefit from the high ballistic velocity in graphene but are degraded by an effective gate capacitance reduced by the quantum capacitance. The gds values, which limit the effective power gain achievable in these devices, are significantly worse than comparable silicon devices due to the properties of the zero-bandgap graphene channel.

Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors

Supercoupling effect prevents the simultaneous formation of inversion and accumulation channels at the two interfaces of ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistor. Our work highlights that short-channel effects enhance supercoupling and turn it into a two-dimensional mechanism. The lateral influence of source and drain terminals is evidenced with experimental data and examined by 2D numerical simulations which reveal the roles of gate length and drain bias. The critical Si-film thickness, below which supercoupling arises, is significantly increased in short-channel transistors. The impact of back-gate and drain bias, BOX thickness, and quantum effects is documented and practical applications are discussed.

Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations.

We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization.

Thermal stability of organic transistors with short channel length on ultrathin foils

We demonstrate an effective design for fabrication of short channel organic transistors (<3μm channel length) on ultrathin 1μm thick substrates that exhibit excellent thermal stability. For short channel transistors, we demonstrate durability up to 170°C, with a theoretical cutoff frequency above 100kHz, and stable performance in cyclic heating tests up to 120°C. We fabricate inverter circuits to investigate their behavior upon heating and show that inverter gain can be improved by 150%. Device performance and topology changes were systematically analyzed after annealing steps to gain better understanding on the mechanism behind the performance change. This report on the thermal stability of short channel transistors on ultrathin films shows good durability at elevated temperatures and paves the way for high frequency imperceptible electronics.

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

Alignment Control of Patterned Organic Semiconductor Crystals in Short-Channel Transistor Using Unidirectional Solvent Evaporation Process

The patterning deposition of highly crystalline organic semiconductor films is a key issue in achieving high-mobility organic thin-film transistor (OTFT) arrays and circuits with practical device dimensions. However, it is generally difficult to obtain uniform crystalline films only on the desired channel regions over a large-area substrate. The alignment control of crystalline domains decreases size variations in the crystalline film. Herein, we present a patterning scheme that can control the alignment direction of solution-grown organic crystals. We employed a simple coating method combining drop casting and lamination coating. By creating a striped pattern of solvent-wettable/solvent-nonwettable regions on a polymer dielectric, we grew nearly uniaxially aligned ribbon-like crystals with a length of 100 $\mu \text{m}$ order within a confined channel region. Bottom-contact short-channel TFTs fabricated on such a stripe pattern showed a high mobility of up to 1.5 cm $^{2}$ /Vs. The proposed method is compatible with the fabrication of OTFTs over an arbitrary large area.

Compact model for short-channel symmetric double-gate junctionless transistors

In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25nm to 500nm and for doping concentrations of 5×1018 and 1×1019cm−3, as well as for Si layer thickness of 10 and 15nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

Analyzing Variability in Short-Channel Quantum Transport from Atomistic First Principles

At the nanoscale, random distribution of impurities causes pronounced device-to-device variability (DDV) in short-channel transistors. This study investigates quantum transport with multiple-impurity scattering in silicon nanoFETs as a function of channel length, doping concentration, and doping profile. The results reveal the microscopic physics of DDV and provide insight for rectifying it, to yield better electronics.

Control and Application of “Coffee Ring” Effect in Inkjet Printing

Inkjet printing is a material-conserving deposition technique used for liquid phase materials. By virtue of convenience, low-cost, flexibility and speediness, inkjet printing has become one of the most promising candidates for fabricating high-quality patterns. In recent years, inkjet printing has aroused wide attention in functional device research area. The coffee ring effect is a common phenomenon in inkjet printing. It directly influences the depositional morphology, which affects the resolution of patterns and the performance of devices. It is very important to research the coffee ring effect in inkjet printing. In this paper, we present the recent research progress of the coffee ring effect in the process of droplet evaporation. Firstly, the forming mechanism and suppressing methods of coffee ring effect are discussed. Secondly, the applications by suppressing or utilizing the coffee ring effect in inkjet printing, such as high quality photonic crystal pattern, high sensitive sensor, semiconductor film, transparent conducting film and short-channel transistor are introduced. Finally, a perspective on the remaining challenges of controlling coffee ring effect in inkjet printing is proposed. The broad research and application of combining the controlling coffee ring effect in inkjet printing and nano-material preparation are discussed. It will be of great significance for patterning, functional device research and 3D printing technology.

Mobility Investigations on Strained 30-nm High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Metal Gate MOSFETs by Geometrical Magnetoresistance Effect

In this paper, we present mobility investigations of strained nMOS and pMOS short-channel transistors with dimensions down to 30-nm gate length. Using the geometrical magnetoresistance (MR) effect, carrier mobility of electrons and holes in the inversion channel of a recent state-of-the-art CMOS technology is presented from linear to saturation operation conditions. The MR effect allows for a more direct access to the carrier mobility compared with the conventional current/voltage and capacitance/voltage mobility derivation methods, in which series resistance, inversion charge density, and effective channel length are necessary to extract the mobility values of the short-channel devices. In another way, the MR effect can help to disentangle the performance gain of the strained state-of-the art devices to changes in channel mobility or device connection, e.g., series resistance effects.

Double-gate junctionless transistor model including short-channel effects

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (VTH), subthreshold slope (S) and drain induced barrier lowering.

Physical mechanism of source and drain resistance reduction for high-performance short-channel InGaZnO thin-film transistors

We systematically study the mechanism of source and drain parasitic resistance reduction in amorphous InGaZnO thin-film transistors. Hall measurement shows that parasitic resistance is reduced by the increase in carrier density regardless of the source and drain processes. The results of photoluminescence, high-angle annular dark field scanning transmission electron microscope (HAADF-STEM), electron energy-loss spectroscopy (EELS), and X-ray photoelectron spectroscopy (XPS) analyses indicate that the fluctuation of In concentration at the InGaZnO surface is responsible for increase in carrier density. A top-gate InGaZnO transistor fabricated with a source drain resistance reduction process shows good short-channel immunity. The short-channel InGaZnO thin-film transistor with reduced source drain resistance is promising as the high-density back-end-of-line transistor in Si LSI.

Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Electrical responses of short-channel organic transistor prepared by solution-processed organic crystal wire mask

We report a formation of a solution-grown single crystal wire mask for the fabrication of short-channel organic field-effect transistor with enhanced dynamic response time. The various channel length, ranging from submicrometer to a few micrometers, were obtained by controlling the concentration of solution and processing conditions. We fabricated p- and n-channel bottom-contact organic field-effect transistors using pentacene and PTCDI-C13, respectively, and static and dynamic electrical characteristics of the devices were investigated. The highest and average field-effect hole mobility values were found to be 0.892cm2/Vs and 0.192cm2/Vs, respectively. The load type inverter based on the short-channel transistor connected with a 2MΩ resistor showed a clear switching response when square wave input signals up to 1kHz were applied at VDD=−60V.

Short-channel graphene nanoribbon transistors with enhanced symmetry between p- and n-branches

Graphene’s unique symmetry between p- and n-branches has enabled several interesting device applications; however, short-channel devices often exhibit degraded symmetry. We examine how graphene nanoribbon geometries can improve transfer characteristics and p–n symmetry, as well as reduce Dirac point shift for highly scaled graphene devices. RF graphene transistors utilizing a multiribbon channel are fabricated with channel length down to 100 nm, achieving 4.5-fold improved transconductance, 3-fold improved cutoff frequency, and 2.4-fold improved symmetry compared with sheet devices. The improved performance is linked to reduced contact effects by modeling the extent of charge transfer into the channel as a function of graphene width.

Inkjet Printing Short‐Channel Polymer Transistors with High‐Performance and Ultrahigh Photoresponsivity

Inkjet-printed short-channel polymer transistors exhibit a high performance (μavg = 1.20 cm(2) V(-1) s(-1) ). With a 50 μm orifice nozzle, polymer transistors with a sub-micrometer (700 nm) channel length are mass-fabricated with good uniformity and reproducibility. In addition, owing to the device geometry, an ultrahigh photoresponsivity up to 10(6) A W(-1) is achieved, which realizes economical, lithography-free photodetectors.

32 nm high current performance double gate MOSFET for low power CMOS circuits

Leakage current increment is a critical challenge in short channel transistors. In this paper, a new high current performance is presented that not only reduces leakage current but also improves the on-current. The key idea in this work is to modify the doping density with inverted-V shape (IVS) in the vertical direction of the channel. By employing IVS doping density, short channel effects such as drain-induced barrier lowering and threshold voltage roll-off improve and the leakage current significantly reduces compared conventional uniform doping double gate MOSFETs. In this paper, by Conduction band energy modification, in weak inversion regime, high potential height is built that carriers cannot inject in to the channel and reduces leakage current. Furthermore, in strong inversion regime, built-in electric field, leads to better channel carriers’ acceleration and transportation which make on-current improvement. So, the high on–off current ratio (Ion/Ioff) is expected.

(Invited) Material Engineering for 7nm FinFETs

Recently, several enabling technologies have become available for integrating non-Si channels on Si wafers, including HKMG with acceptable trap densities, aspect ratio trapping, and low temperature epitaxy with in-situ doping. This considerably broadens the list of potential candidate materials for the 7nm technology node in search of exceeding performance of Si FinFETs.The search for the alternative channel materials is often motivated by high levels of carrier mobility in bulk material. Some promising demonstrations have been done with long channel transistors. However, the bulk carrier mobility is not relevant for performance of the short channel transistors. The target channel length for the 7nm node is about 15 nm, with most of the carriers exhibiting ballistic transport without experiencing scattering events when moving from source to drain. The ballistic transport favors materials with lighter effective carrier mass in terms of the driving current strength. On the flip side, such materials exhibit higher off-state leakage currents via band-to-band tunneling and direct source-to-drain tunneling mechanisms. So, instead of being guided by the bulk carrier mobility numbers, a more appropriate approach is to evaluate the trade-off between the on-state and the off-state current levels for the particular combination of material properties and transistor design rules.In this work, we assume that the process-related issues such as defects can be resolved over time and focus on performance of defect-free materials, with performance determined by fundamental material properties. This way, we can get the upper bound on performance for each candidate material and see if it is worth pursuing in terms of struggling through laborious process integration.Besides the on-state and off-state currents, several other key metrics are included into the trade-off analysis, such as self-heating and the ability to withstand and dissipate the heat, and parasitic R and C of the MOL.The comparative analysis of several candidate channel materials is performed considering four technology flavors: HP, SP, and LP logic, and the I/O transistors. The appropriate modeling methodologies are introduced to cover these materials and the target design rules.