Short-channel Metal-oxide-semiconductor Field-effect Transistor Research Articles

Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.

An accurate compact model to extract the important physical parameters of an experimental nanoscale short-channel SOI MOSFET

A new compact model is introduced to determine the drain current of an experimental short-channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) analytically. The effective physical parameters of the experimental nanoscale SOI MOSFET were successfully extracted for the first time using an efficient search algorithm named particle swarm optimization (PSO) as a link between the analytical drain model and the experimental data. Seven important parameters, viz. the drain-induced barrier lowering, subthreshold swing, additional resistance at the source terminal, carrier velocity, low-field carrier mobility, and threshold voltage, were sought using the PSO algorithm to obtain the best fitness value. The results revealed that the application of this PSO strategy achieved an excellent match between the proposed drain current model and experimental data notwithstanding the initial values of the fitting parameters. Also, the internal node capacitances of the short-channel SOI MOSFET were successfully extracted for use in compact models of its small-signal operation.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor**Project supported by the National Natural Science Foundation of China (Grant No. 61274112).

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor (MOSFET) are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a short-channel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

An in-depth study on WENO-based techniques to improve parameter extraction procedures in MOSFET transistors

WENO-based techniques, along with some particular polynomial interpolation procedures, have been employed to improve parameter extraction in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), in particular for the determination of the threshold voltage. The limitations detected in conventional numerical methods to calculate derivatives of experimental data are overcome with this new application of WENO-based techniques. The numerical noise that comes up in the experimental and simulated data usually employed to characterize MOSFETs transistors is strongly reduced. The need for an accurate determination of the threshold voltage motivates the use of this advanced numerical approach that solves many of the issues that affect the conventional parameter extraction procedures currently in use in the microelectronics industry. In addition, also the influence of DIBL effects on the threshold voltage in short channel MOSFETs has been analyzed with this smart weighted ENO procedure.

Physical origin of gate voltage‐dependent drain–source capacitance in short‐channel MOSFETs

For the first time, it is revealed that the physical origin of the gate–source voltage (V gs)-dependent drain–source capacitance in short-channel metal–oxide semiconductor field-effect transistors (MOSFETs) comes from the depletion capacitance components between the drain and channel end in the saturation region. On the basis of this origin, it is newly found that the V gs-dependent channel resistance should be connected in series with the drain–source capacitance to model the high-frequency (HF) response of the intrinsic output capacitance. The accuracy of an improved MOSFET model, including the channel resistance, is validated by observing the excellent agreement with the measured S-parameters in the wide range of V gs up to 40 GHz.

Pseudosymmetric bias and correct estimation of Coulomb/confinement energy for unintentional quantum dot in channel of metal-oxide-semiconductor field-effect transistor

We describe a measurement method that enables the correct estimation of the charging energy of an unintentional quantum dot (QD) in the channel of a metal-oxide-semiconductor field-effect transistor (MOSFET). If the channel has a single dominant QD with a large charging energy and an array of stray QDs with much weaker charging, this method eliminates the additional voltage drops due to stray QDs by regarding the stray QDs as series resistors. We apply this method to a short-channel MOSFET and find that the charging energy of the dominant QD can indeed be smaller than the size of the Coulomb diamond.

Modelling of Hot-Electron Energy in Short-Channel MOSFETs by Electrical Method

Channel hot-electron (HE) energy in short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) is estimated based on electrical characterization. The HE assisted gate leakage is monitored, and its energy dependent tunnelling probability is calculated, from which the excess energy of HE is estimated. The credibility of the proposed method is supported by the experimental and theoretical results, and its accuracy in ultra-small-feature-size device application is also discussed.

Electron mobility in scaled silicon metal-oxide-semiconductor field-effect transistors on off-axis substrates

Off-axis silicon wafers promise monolithic integration of III-V optoelectronics with silicon microelectronics. However, it is unclear how miniaturization affects electronic device performance on off-axis substrates. We present the fabrication and characterization of metal-oxide-semiconductor field-effect transistors (MOSFETs) with different gate lengths on regular Si(100) and 4° off-axis wafers. The field-effect electron mobility in the off-axis devices is lower than in their (100)-wafer counterparts with equivalent gate length. Monte Carlo simulations have reproduced the experimental data and demonstrated that the mobility degradation in off-axis devices stems from enhanced electron scattering from the Si/SiO2 surface roughness. Short-channel MOSFETs on (100) and off-axis substrates perform comparably.

Kinetic investigation of electron–electron scattering in nanometer-scale metal- oxide-semiconductor field-effect transistors

The effects of electron–electron scattering on the electron energy distribution, as well as substrate and gate currents in short channel MOSFETs (metal-oxide-semiconductor field-effect transistors) are explored using the convective scheme, or CS, a method of characteristics. Effects of electron–electron scattering are explored for a MOSFET with uniform doping in the channel as well as for an asymmetric device structure, a focused-ion-beam (FIBMOS) transistor, for both 70 nm and 250 nm channel length devices. Effects of electron–electron scattering on a standard 35 nm channel length MOSFET are also included. The high substrate doping that is required for such short channel length devices leads to large electric fields. The purpose of the FIB implant is to improve hot-carrier reliability by reducing the electric field in the channel. Electron–electron scattering increases the amount of electrons in the tail, despite the fact that the applied potential is significantly below the threshold for injection of electrons into the gate oxide. The ratio of gate-to-substrate current, Ig/Isub, is investigated as an indicator of the level of degradation. At such short channel lengths, there are degrading and non-degrading components of gate and substrate current. The non-degrading components of gate and substrate current correlate strongly, so that the ratio of Ig/Isub is an efficient indicator of device degradation. The energy thresholds for impact ionization and for emission of electrons into the gate oxide are crucial in determining the ratio of these currents. The substrate and gate currents obtained indicate that hot-carrier effects continue to be an issue for device performance, even for nanometer-scale devices. The density of electrons is higher at very short channel lengths due to the need to have shallow junctions and leads to a greater amount of Coulomb collisions. Increased Coulomb collisions may lead to strongly reduced lifetimes in nanometer-scale devices.

Effect of Three Normal Mechanical Stresses on Electrical Characteristics of Short-Channel Metal–Oxide–Semiconductor Field Effect Transistor

The change in electrical characteristics due to mechanical stress is studied for short-channel metal–oxide–semiconductor field effect transistors (MOSFETs) fabricated on (001) substrate in advanced 65 nm technology. An experimental trial is carried out to investigate the effect of three independent components of mechanical stresses orthogonal to one another on drain current and threshold voltage using a pin-pressing apparatus and the cantilever method. The change in drain current agrees with the signs and magnitudes shown in the literature for surface stress on the (001) plane. On the other hand, the change versus stress vertical to the plane shows a peculiar phenomenon for pMOSFET. That is, the change decreases with the expected rate up to 90 MPa, but increases rapidly above 450 MPa. Although the physical mechanism is unclear at present, simultaneously generated biaxial horizontal strains possibly cause this peculiar phenomenon.

A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line

A compact physics-based nonquasi-static (NQS) metal-oxide-semiconductor field-effect transistor (MOSFET) model with the equivalent nonlinear transmission line (TL) representing channel carriers drift-diffusion transport is developed and implemented in the simulation program with integrated circuit emphasis (SPICE) program. An auxiliary subcircuit is described, which efficiently solves the channel surface boundary potentials without the need for employing separate iterative algorithms. The short-channel effects and the quantum effects are efficiently included owning to a surface-potential-based modeling approach. In comparison with other Berkeley short-channel IGFET model 3 (BSIM3)-based NQS MOSFET models, it is shown that the new NQS TL model has the advantages in higher accuracy and substantially fewer number of model parameters. From comparison with a two-dimensional device simulator, it is demonstrated that the new NQS TL model can accurately predict dc, ac, and transient behavior of long- and short-channel n-type MOSFETs in all operational regions and for the input signal frequencies up to 10 f/sub T/ values, using only one set of model parameters.

Hot-electron injection in stacked-gate metal-oxide-semiconductor field-effect transistors

Hot-electron injection in high dielectric constant stacked-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) is studied theoretically by combining a hybrid Monte Carlo/iterative simulation of hot carrier transport with a transfer-matrix calculation of the transmission probability through the insulators. It is shown that the reduced potential barrier between the silicon and the high dielectric constant material results in high gate currents in short channel MOSFETs even at low drain voltages. The structure may therefore find applications in electrically erasable programmable read-only memory devices.

Ionizing radiation-induced effects in an ion-implanted MOSFET: a two-dimensional analytical model

A two-dimensional analytical model of a metal-oxide-semiconductor field-effect transistor (MOSFET) has been developed to examine theoretically the effect of ionizing radiation on the characteristics of an ion-implanted MOSFET. The radiation-induced change in the flat-band voltage have been utilized to estimate the characteristics of the device in the post-irradiated condition. The model has been used in conjunction with the Level-2 models of the SPICE package for estimating the I D – V D characteristics of the MOSFET in the post-irradiated condition. The model has been validated by reported experimental results. The two-dimensional nature of the model enables it to characterize even short-channel MOSFETs in the pre- and post-irradiated conditions.

Simulation of Temperature Dependence of Microwave Noise in Metal-Oxide-Semiconductor Field-Effect Transistors

We present results of a two-demensional (2D) numerical simulation of high-frequency noise in a short-channel metal-oxide-semiconductor field-effect transistors (MOSFET). Conventionally this noise in MOSFETs is treated as a thermal noise with a rather slow temperature dependence of the noise spectra. On contrary, the results obtained indicate that this dependence is more of an exponential kind, typical for a shot noise. Shot noise is conventionally related to a forward biased p-n junction where the current is mostly due to diffusion in the quasi-neutral region. We therefore speculate that most likely in short channel MOSFETs most of the high-frequency noise is produced not in the cut-off region of the channel but near the source side of the channel where diffusion current component is dominant.

Analytical Calculation of Subthreshold Slope Increase in Short-Channel MOSFET's by Taking Drift Component into Account

Modeling of the subthreshold slope S and the threshold voltage V T has been done based on the fundamental equations governing the metal-oxide-semiconductor field-effect transistor (MOSFET). Taking the drift as well as the diffusion component of the current into account resulted in a physically complete description of the short-channel effect. The method calculates the potential from the 2D Poisson equation, the minority carrier density from the continuity equation and the weak inversion current density from the drift-diffusion model. As an example, the detailed calculation of the S factor is given. The new closed-form formula for S includes the L dependence in an accurate way.

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

Interface trap densities at gate oxide/silicon substrate (SiO2/Si) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

Comparison of Measurement Techniques for Gate Shortening in Sub-Micrometer Metal Oxide Semiconductor Field Effect Transistors

In this paper, various methods of evaluating the electrical channel length change (or gate shortening) as a result of applied gate voltage in sub-micrometer metal oxide semiconductor field effect transistors (MOSFETs) are investigated and the method best suited for such short channel length devices is reported. Studies were performed on n-channel transistors (n-MOSFETs) fabricated using X-ray and optical lithography and having channel lengths in the range of 0.4 to 4 µm and 1.5 to 10 µm respectively. The effective channel lengths were extracted from the current-voltage (I-V) measurements. The measurements were made for different low and high sets of gate voltages. In comparing various methods it was found that the method due to Terada and Muta, and Chern et al. gave accurate results consistently for short channel MOSFETs, whereas the Whitfield method gave accurate results only for larger channel length MOSFETs. The accuracy of the Whitfield method is sensitive to applied gate voltage during I-V measurements. The Peng and Afromowitz method is unsuitable for finding the effective channel length of sub-micrometer MOSFETs especially if the MOSFETs have high values of external resistance.

Enhanced model for short channel MOSFETs

The accuracy of the existing metal-oxide-semiconductor-field-effect-transistor (MOSFET) models used in simulations of the integrated circuits can be enhanced by restoring some of the device physics which has previously been eliminated in the original models. The model modifications include an improved treatment of mobility degradation phenomena and an improved approximation for the saturation voltage. These modifications result in excellent agreement with the experimental data for both n- and p-channel transistors having effective channel lengths as small as 0.5 μm. In contrast to previous models the agreement with the measured data is achieved by using a physically acceptable value for the charge carrier saturation velocity and a smaller number of fitting parameters.

Optimal design of an electret microphone metal-oxide-semiconductor field-effect transistor preamplifier.

A theoretical noise analysis of the combination of a capacitive microphone and a preamplifier containing a metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-value resistive bias element is given. It is found that the output signal-to-noise ratio for a source follower and for a common-source circuit is almost the same. It is also shown that the output noise can be reduced by making the microphone capacitance as well as the bias resistor as large as possible, and furthermore by keeping the parasitic gate capacitances as low as possible and finally by using an optimum value for the gate area of the MOSFET. The main noise source is the thermal noise of the gate leakage resistance of the MOSFET. It is also shown that short-channel MOSFETs produce more thermal channel noise than longer channel devices.

Velocity-Saturated Characteristics of Short-Channel MOSFETs

A theory is developed for the I-V characteristics of metal oxide semiconductor field-effect transistors (MOSFETs) when the channel fields are sufficiently high to cause appreciable saturation of the carrier drift velocity. The full velocity-field curve for bulk silicon is used with the base value adjusted to account for surface scattering effects. Use of this form gave the best fit to experimental data. Using some simple expansions to reduce the rather complex integral produces a useful analytic result, which gives a continuous description from the square law results for long-channel devices throughout the whole range of velocity-saturated operation in short-channel devices. For the first time the electron temperature has been introduced as the parameter, which increases the channel charge at pinch-off, decreases the saturation voltage, and increases the channel field at the pinch-off point as the current (and hence bias voltages) is increased. The effects of series resistance and surface roughness scattering are incorporated into the analytic formulation. We compare the results with experimental submicron devices and find excellent agreement.