Shallow Trench Isolation Structure Research Articles

Heterojunction bipolar transistor featuring a stressed implanted collector: Defects formation and impact on functionality

Optimization of Heterojunction Bipolar Transistors is crucial for improving RF capabilities of modern BiCMOS technologies. Fully-implanted collectors are meant to reduce fabrication complexity and Super Shallow Trench Isolation (SSTI) structures are used to reduce the consequent high base–collector capacitance. Ion implantation can induce lattice defects in silicon and carbon plus phosphorus co-implantation helps reducing them, even if it cannot avoid formation of dislocations generated by bad recrystallization of the implantation-induced amorphous silicon layer. Defects within the device are known to impact functionality and must be avoided. Understanding of the interaction between implantation-induced amorphization and substrate stress due to isolation structures is required for ensuring a reliable integration. Amorphous layer positioning with respect to substrate surface is investigated as the main defect-generation mechanism. Incomplete surface amorphization is shown to induce multiple types of dislocations affecting device functionality. Total surface amorphization ensures almost ideal current characteristics. Silicon clusters appear at high phosphorus/carbon ratios with no impact on functionality. Stress induced by isolation structures is not responsible for dislocations generation but modulates speed of the recrystallization fronts, impacting defects placement.

Junction Engineering-Based Modeling and Optimization of Deep Junction Silicon Single-Photon Avalanche Diodes for Device Scaling

A silicon single-photon avalanche diode (Si-SPAD) with a deep multiplication zone was fabricated using 0.11- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -CMOS technology. Deep n-well (DNW) implantation with three energy levels was performed to prepare a deep junction, and the highest breakdown voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BR}}$ </tex-math></inline-formula> ) and lowest dark count rate (DCR) were obtained at the highest DNW implantation energy. In addition, devices with different structures were manufactured: a shallow junction, deep junction with mask DNW, deep junction with mask DNW without shallow trench isolation (STI), and deep junction with blank DNW. The blank DNW structure exhibited a lower edge breakdown risk and less deviation between samples compared to those of mask DNW structure in terms of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BR}}$ </tex-math></inline-formula> and DCR. Moreover, a new edge breakdown risk was observed between DNW and p-well (PW) in the DNW blank structure, which could be alleviated by adjusting the PW sizes. According to the measurement results, the STI structure was preferable in terms of fill factor. Measurements were obtained from real fabricated test device structures, and technology computer-aided design (TCAD) for various factors associated with Si-SPADs with deep multiplication structures was performed.

(Digital Presentation) Research on Single Wafer RCA Clean in High Aspect Ratio Trenches

High aspect ratios trench are commonly used in shallow trench isolation (STI) or Gate Poly-silicon structures by dry etching of a silicon substrate. During the dry etching process, polymerization residues are produced inside the trench. These polymerization residues must be removed before the next deposition process. Watermarks might also form by poor drying after the wet cleaning process of high aspect ratio structures, which can seriously affect the next process. In this paper, we show the performance of single wafer RCA cleaning technology in high aspect ratio structures. Polymer residues can be removed by diluted HF and SC1 with megasonic technology, without the appearance of watermarks after drying. This study focuses on polymerization residues and watermarks using inline defect detection to qualify the performance of single wafer RCA clean. Yield is the final verification for proving the single wafer RCA clean.

Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

This article presents a study of Single Photon Avalanche Diodes (SPAD) implemented in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology based on transient TCAD simulations and Dark Count Rate (DCR) measurements. The integration of SPAD in this technology is currently being studied. This work allows for a better understanding of the mechanism behind the quite high DCR measured at relative low excess bias voltages with the initial FD-SOI SPAD design (≈500 Hz/µm2 at 5% excess bias voltage). In this study, a TCAD transient simulation methodology is introduced to better understand SPAD behavior during the avalanche process. TCAD simulations revealed that Shallow Trench Isolation (STI) structures within the active area have a negative effect on avalanche quenching, because of slower carrier evacuation with possible occurrence of secondary avalanches in series. Based on this analysis and on previous optimization works, we propose a new architecture of the FD-SOI SPAD combining several modifications to achieve a lower DCR (≈20 Hz/µm2 at 5% excess bias voltage measured with passive quenching).

Shallow trench isolation structure design for through‐silicon vias stress reduction

AbstractThrough‐silicon vias (TSVs) technology provides an effective approach for “more than Moore,” however, the stress caused by TSVs may cause the surrounding devices to be squeezed and cause failure. In order to reduce the thermal stress of the TSV while innovatively considering the anisotropy of the silicon substrate, a shallow trench isolation (STI) structure was designed, and the influence of the shape and size of the STI on the stress reduction effect was studied. The research results show that the petal‐shaped STI structure reduces the thermal stress caused by TSV by 26% and the KOZ area by 31%, which provides a solution for reducing the stress and KOZ area in the anisotropic silicon substrate.

Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

Comprehensive Stress Effect of Thin Coatings and Silicon-Carbon Lattice Mismatch on Nano-Scaled Transistors with Protruding Poly Gate.

Enhancing the mobility in metal-oxide-semiconductor field-effect transistors (MOSFETs) with narrow channel widths is highly sensitive to the stress effects of Si channel when related advanced strain engineering is introduced and is compatible with semiconductor processes. In practice, layouts have significant effect on the device performance, especially for the protruding gate width on shallow trench isolation structures. The geometric parameter is investigated by systematically analysing an n-channel MOSFET composed of silicon-carbon (SiC) stressors embedded in the source and drain (S/D) regions and a tensile contact etch stop layer (CESL) using three-dimensional finite element simulation. Tensile CESL (1.1 GPa) and a SiC S/D stressor with a carbon mole fraction of 1.65% are loaded on the structure. The difference in the interactive percentages between the mechanical bending effect of the CESL from the top of the poly gate and the downward force of the CESL adjacent to the spacer sidewall of the gate occurs when the protruding gate width is increased. Results indicate that mobility was highly enhanced by approximately 72.5% at a width of approximately 0.2 μm. The mechanical bending effect becomes dominant when the gate width is more than 0.2 μm. Consequently, the mobility gain decays and consequently converges toward a constant.

The Adhesion and Removal Mechanism of Ceria Particles for STI Post-CMP Cleaning Process

Chemical mechanical planarization (CMP) is an essential step to remove overburden oxide surface and form STI (Shallow Trench Isolation) structures during the semiconductor manufacturing. This is usually carried out with ceria slurry due to high selectivity between oxide and nitride surfaces. However, strong ceria adhesion to oxide surface is a major concern, as it cannot be removed easily during the post-CMP cleaning step. Generally, it is performed by a combination of physical and chemical cleaning. Conventional cleaning solutions such as DHF (Dilute Hydrogen Fluoride), SC1(NH4OH: H2O2: H2O mixture), SPM (H2SO4:H2O2 mixture) solutions are used with optimized concentrations and sequences with the support of physical forces such as PVA brush scrubbing or megasonic. However, the adhesion and removal mechanism of ceria particles from the oxide surface is not clear yet. The ceria particles would attach to the oxide to the surface may be due to electrostatic interaction or valence (Ce3+/Ce4+) effect or chemical bonding linkage of Ce-O-Si. These interactions are strongly affected and changed based on the pH of ceria used for polishing. In this work, it was emphasized to identify the specific individual mechanisms of physical cleaning and chemical cleaning in removing ceria particles from the oxide surface. Two types of physical cleanings, one is the non-contact mode (megasonic) cleaning and another one is contact mode (PVA brush) cleaning, were performed. The effect of different chemicals on removing the ceria particles was also performed. The key mechanism for the ceria particle cleaning was hypothesized. TEOS coupons (4´4 cm) were polished with ceria slurry (100nm) of pH 4 and 8, containing no additives. The optimization of physical cleaning experiments, performed with only DIW, was carried out with a single wafer megasonic cleaning (Akrion, 0.83MHz) and brush cleaning tool (lab designed pin type brush). Chemical cleaning was performed with various chemistries (SC1, DHF, SPM) to compare and understand the ceria removal performance from the oxide surface. The particles before and after cleaning were observed by FESEM and optical microscopy. To understand chemical interactions, the polished samples were analyzed for XPS, ATR FTIR, and Raman analysis before and after cleaning. The type of chemical interactions before cleaning and their modifications with the type of chemistry used were discussed. The comparative study of physical cleaning (megasonic vs. brush) were performed for the removal of ceria particles attached to the surface after polishing with slurries of pH 4 and 8. It was observed that the polished oxide surface was more contaminated with ceria in the pH 8 than in pH 4. Megasonic cleaning was able to remove partially, whereas brush scrubbing removed completely for pH 4 samples. However, the ceria particles from pH 8 samples were strongly attached not removed by megasonic and partially removed by brush cleanings. It could be expected that particles would attach electrostatically at pH 4, whereas chemically through Ce-O-Si bond at pH 8. It may be necessary to use chemical forces to break the chemical bonds between ceria-silica. It was suspected that the change of valence of ceria before and after cleaning with cleaning chemistries also would play a key role. Hence different chemistries were used to check the removability of ceria. The samples before and after cleaning were analyzed with different techniques to understand the chemical forces required to break the ceria-silica bonding. Detailed hypothesis for the ceria removal was explained by their chemical interactions with different chemistries.

Hot-Carrier-Induced Degradation and Optimization for Lateral DMOS With Split-STI-Structure in the Drift Region

The lateral double-diffusion MOS with split shallow trench isolation structure (split-STI LDMOS) in the drift region has been investigated under two hotcarrier stresses including the maximum bulk current stress (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> ) and maximum operating gate stress (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> ). For the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition, the main damage point causing the degradation of RON is found at the STI corner closest to the source with the interface state generation. In addition, the hot hole injection is found at the edge of the shrinking poly-gate region. For the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> stress condition, the main damage point causing the degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> is found at the two STI corners with interface state generation. Due to the more serious degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition is regarded as the worst-case stress condition. The novel structure with the H-shape STI in the drift region is proposed. It is demonstrated that the H-shape STI structure is effectively helpful to alleviate the hot-carrier degradation without altering the tradeoff between the OFF-state breakdown voltage and specific ON-resistance.

Silica Nano-particle Anneal Treatment and Its Effect on Chemical Mechanical Polishing

Introduction Chemical mechanical polishing is the only one technology to obtain global planarization, which is widely applied to polish silicon, copper dual damascene structure, high/low K dielectric materials, tungsten plugs, poly-silicon gates and shallow trench isolation structure. SiO2 is widely used as abrasive for its superior properties like stability, suspension property and low viscosity There are lots of studies on silica properties. However, the detailed silica surface, inner characteristic and its effect on polishing performance are still unclear. we must also explore the silica nano-particle tiny structure difference, so we designed an experiment that we anneal the colloid silica and re-dispersed it to analyze the variety of particles properties and its influences on CMP performance.

120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process

In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.

Characterization of Ammonium Silicate Residue during Polysilazane (PSZ) Dry Etching in NF3/ H2O Gas Chemistry

For 28nm NAND flash memory, the aspect ratio of shallow trench isolation (STI) becomes large, and it makes difficult to fill STI structure by conventional oxide film without void formation. Several gap-fill methods such as high density plasma (HDP) and thermal chemical vapor deposition (CVD) are widely accepted, but they are difficult to make gap fill without void because of gap-fill margin. Recently, STI fill has been tried with polysilazane (PSZ) based inorganic spin-on dielectric (SOD) film. PSZ oxide has its good gap-fill ability, low moisture content and high etching resistance. However, PSZ oxide would produce amine etch residue during the NF3 dry etching process because of NH3component in PSZ oxide. For preventing this resudue, it is very important to control process parameters affecting the chemical reaction because the etch rate, and the surface quality depend upon the process reaction. During the STI etching back process, other layer also exposed. So, selectivity between other oxide must be considered. In this study, we have employed plasma dry etching of nitrogen trifluoride (NF3) and H2O mixtures. We studied the effect of the gas chemistry on the etching of oxides. The materials used for these experiments were thermally grown SiO2 (1000Å, 10000Å), PSZ oxide (500Å), TEOS (315Å) and ALD oxide (300Å). Samples of size 25 x 25 mm were cleaned first in diluted SC-1 [NH4OH(25%): H2O2(38%): DIW =1:2:50] at 60°C for 10 min. The etching mechanism of PSZ oxide was investigated in plasma activated NF3/H2O gas. This process generates ammonium hexafluorosilicate ((NH4)2SiF6) as a by-product. By-products were formed on the PSZ surface which was confirmed by observing N–H, NH4+ and SiF6 2-peak in ATR-FTIR spectrum. These peaks are representative of (NH4)2SiF6 powder composition. Etch rates of several SiO2 were reported as a function of H2O ratio, substrate temperature, and pressure. NF3/H2O mixtures were excited using pulsed RF plasma. The NF3 flow rate for all experiments was kept at 150 sccm. The temperatures were varied from 8 to18ºC, the chamber pressures from 7 to 9 Torr., the H2O flow rates from 1500 to 2500 sccm and process times from 20 to 100 sec. Helium was used as a carrier gas. After dry etching, an annealing process was performed. The reaction mechanism was proposed by analyzing the oxide layer surface. We used an ellipsometer to measure the oxide thickness for evaluation of the etch rate. Also, various analyzing tools such as SEM, contact angle analyzer, and FT-IR were used to characterize the surface contaminants. The optimized drying process provides the high selectivity without any residue formation.

Structural Optimizations of Silicon Based NMOSFETs with a Sunken STI Pattern by Using a Robust Stress Simulation Methodology.

As the strained engineering technology of metal-oxide-semiconductor field effect transistors (MOSFET) is scaled beyond the 22 nm node critical dimension, shallow trench isolation (STI) becomes one of the most important resolutions for isolate devices to enhance the carrier mobility of advanced transistors. Several key design factors of n-type MOSFET (NMOSFET) under the resultant loadings of STI structures and contact etching stop layers are sensitively analyzed for silicon channel stress via finite element method-based simulations integrated with the use of design of experienmnts. NMOSFETs with 15 nm deep sunken STI have achieved a ~5% mobility enhancement as compared with a regular STI shape. By adopting simulation-based factorial designs, we have determined that the design factor of recess depth in STI is a critical factor influencing device performance. Moreover, a response surface curve on carrier mobility of NMOSFET under a consideration of combining the sunken STI and source/drain lengths is further presented in this research.

Shallow Trench Isolation Chemical Mechanical Planarization: A Review

Electrical isolation of the billion or so active components in each integrated device is achieved using shallow trench isolation (STI) which requires chemical mechanical planarization (CMP) involving silicon dioxide removal at a high rate and stopping on an underlying silicon nitride film. Several colloidal slurries with various additives can yield the desired high rate selectivity between the oxide and nitride films during CMP while maintaining an acceptably low nitride rate. Here, many of such high selectivity STI CMP slurries described in the literature are reviewed along with the characteristics of the colloidal dispersions like the abrasives, additives, the interactions between them and with the films being planarized and the associated pH range in which the high selectivity is observed. The mechanisms proposed to explain the high reactivity of ceria with oxide, the role of additives in suppressing the nitride removal rate and resulting high selectivity are discussed. Reduction of a multitude of defects in post-CMP processed STI structures still remains an important challenge, especially as the feature sizes continue to shrink.

A Low Dark Leakage Current High-Sensitivity CMOS Image Sensor With STI-Less Shared Pixel Design

A CMOS image sensor with a low dark current and high sensitivity is developed with shallow trench isolation (STI) less shared pixel. By sharing in-pixel transistors, such as the reset transistor, select transistor, and source follower amplifier, each pixel achieves a high fill factor of 43% and a high sensitivity of 144.6 ke <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /lx · s. In addition, compared with a conventional image sensor which has the STI structure in the pixel for isolation, the developed image sensor achieves a relatively low dark current of 104.5 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /s/pixel (median), corresponding to a current density J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dark</sub> of approximately 30 pA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 60 °C. This is a low value and the consequence of not using STI as pixel isolation. Both types of pixels, namely the conventional and the proposed active pixel sensor have the same pixel size of 7.5 × 7.5 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and are fabricated by the same process. The developed imager with STI-less shared pixel obtains sufficiently good responses at 400 to 900 nm, and, particularly, a peak QE of 68% at 600 nm. This is suitable for scientific applications.

On the Origin of Anomalous Off–Current Under Hot Carrier Stress in p-Channel DDDMOS Transistors With STI Structure

This letter investigates the abnormal off-current behavior induced by hot carrier stress (HCS) in p-channel double diffused drain metal-oxide-semiconductor transistors with a shallow trench isolation (STI) structure. According to ISE-TCAD simulation, the electric field at the drain-side corners of the high-voltage n-well (HVNW) adjacent to the STI trench is stronger than the electric field in the channel center in width direction. Moreover, because a nitride layer acts as a buffer in STI, the electrons generated by impact ionization at the corners of the HVNW can be easily trapped in the nitride layer or at the liner oxide/nitride layer interface. Furthermore, the extension of electron trapping in STI from drain to source during HCS forms the off-current conductive path. Based on the charge pumping measurements at different operation conditions, this path formation is further demonstrated by the comparisons of charge pumping measurements between initial state and after HCS.

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor (FinFET) is a winning combination to further boost the performance of future CMOS devices.Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active regions, using nanometer scale trenches with high aspect ratio (>3) in order to eliminate (111)-oriented defects (such as threading dislocations, twins or stacking faults) on the sidewalls. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy (SA-MOVPE). Silicon 300mm wafers substrates patterned with ~300nm deep Shallow Trench Isolation (STI) structures are used with trenches having typical widths ranging from 500 nm down to ~20nm.We report here on the SA-MOVPE growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. The structures are fully characterized by Scanning and Transmission Electron Microscopy, Atomic Force Microscopy, X-Ray Diffraction, Secondary Ion Mass Spectroscopy and Scanning Spreading Resistance Microscopy. We demonstrate the dependence of the material quality and trench filling upon different sets of growth conditions.We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach for advanced III-V based logic devices or III-V based photonic applications on a common Si platform.

Simulation-based sensitivity estimation of the geometric effect of poly gates on nanoscale n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon alloy

The mobility enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) using narrow gate lengths and channel widths is sensitive to the stress effects of silicon channels related to advanced strain engineering. The layout pattern of MOSFETs significantly influences the device performance, particularly the protruding gate width on shallow trench isolation structures. This paper investigates the geometric construction of an n-channel MOSFET composed of silicon–carbon stressors embedded in source/drain regions. The stressors have a 1.65% carbon mole fraction and a 1.1GPa tensile contact etch stop layer. Finite element analysis and analysis of variance were used to determine the bending effect of protruding gate widths on the MOSFETs. Results show that the main variation parameters are channel lengths and protruding gate widths, which determine the improvement in device performance. These results can serve as guidelines of stress impacts for predicting the next-generation node technologies of layout patterns.

TCAD 툴을 이용한 제안된 얕은 트랜치 격리의 시뮬레이션

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

Chemical mechanical planarization of patterned InP in shallow trench isolation (STI) template structures using hydrogen peroxide–based silica slurries containing oxalic acid or citric acid

The fabrication of an InGaAs n-channel in complementary metal oxide semiconductors (CMOS) requires an intervening layer of Indium Phosphide (InP) that should be planarized using chemical mechanical planarization (CMP) before deposition of the InGaAs layer. The InP CMP process has to provide good InP removal rates (RRs) (100–200nmmin–1), very low oxide loss, low dishing and minimal or no phosphine evolution. In this work, it is shown that aqueous slurries containing 3wt% silica, 1wt% hydrogen peroxide and 0.08M oxalic acid or citric acid satisfy these requirements. Cross–sectional scanning electron microscope (SEM) images showed that InP in the shallow trench isolation structures was planarized and scratches, slurry particles and smearing of InP on the wafers were absent. Additionally, wafers polished at pH 6 showed very low dishing values of about 12–15nm, determined by cross–sectional SEM.