Shallow Trench Isolation Structure Research Articles

Void-free filling of spin-on dielectric in 22nm wide ultrahigh aspect ratio Si trenches

The authors demonstrate fabrication of ultrahigh aspect ratio nanotrenches, made by nanoimprint lithography and dimension reduction, as test bed shallow trench isolation structures for the 22nm semiconductor node. Polysilazane based spin-on dielectric (SOD) material is spin coated into the nanotrenches, of 22nm width and aspect ratio over 30, to evaluate gap filling property. Fourier transform infrared spectroscopy analysis is used to characterize the curing properties of the SOD, showing that the material can be cured in oxygen at temperatures of 600°C and higher. Transmission electron microscopy images indicate that the filling is complete and void-free along the entirety of the trench.

Behavior of hot carrier generation in power SOI LDNMOS with shallow trench isolation (STI)

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density ( J E) and impact ionization generation rate ( R II) distributions in the devices. The high R II site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.

Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure

In this paper, early-stage hot-electron generation is shown to inject electrons into the shallow trench isolation (STI) edge above the drift region that causes the linear-region drain current to increase abruptly in the first moment of the stress for P-LDMOS transistors. After this early-stage carrier trapping, the transistor exhibits normal hot-carrier degradation during the following stress period. To further study this phenomenon, the geometry and the doping profile of the drift region near the STI edge and the polysilicon gate doping area are changed to investigate the initial IDLIN increase. Two-dimensional device simulator is used to analyze the experimental results. It is proven that the amount of current increase strongly depends on the distance from the maximum impact ionization generation rate point to the STI.

STI Post CMP Cleaning Solution Development

Shallow Trench Isolation (STI) is the standard isolation method for fabrication of submicron CMOS devices. Ceria based slurries are often used for the chemical mechanical planarization (CMP) of STI structures. It is essential therefore, to clean the structure after the CMP process to remove the ceria and other organic residues, usually resulting from the slurry. In this paper, post CMP cleaning of STI wafers with a specially formulated clean solution has been discussed.

Shallow trench isolation liners and their role in reducing lattice strains

Three spin-on dielectric (SOD) shallow trench isolation (STI) structures were studied: nitride liner, nitride liner with anisotropic amorphous silicon (a-Si) bottom fill, and nitride liner with thin conformal a-Si. All samples received the same SOD material conditions and final thermal oxidation. Convergent beam electron diffraction determined the induced STI strain and has been shown to accurately measure strain on 60nm active areas. The results revealed effects that the liners have in balancing stress induced by volume shrinkage of the SOD. The conformal a-Si liner decreased the shear force that causes dislocations that form at the bottom corners of STI structures.

Real-space strain mapping of SOI features using microbeam X-ray diffraction

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.

Nanoscale Stress Field Evaluation with Shallow Trench Isolation Structure Assessed by Cathodoluminescence Spectroscopy, Raman Spectroscopy, and Finite Element Method Analyses

Stress engineering related to the LSI process is required. With shallow trench isolation (STI) structures, a high stress field causes a variation in electrical characteristics. Although stress fields in a Si substrate can be detected by Raman spectroscopy, no effective technique has been reported for the measurement of nanoscale stress fields in a dielectric material used for STI filling. Recently, we have reported that “cathodoluminescence (CL) spectroscopy” enables us to detect nanometer-scale stress fields in LSI structures. In this study, we performed the first estimation of the stress fields with a STI structure by CL and Raman spectroscopy, as well as finite element method (FEM) calculation. We were able to repeatedly acquire clear stress distributions by CL and Raman spectroscopy. Moreover, CL, Raman, and FEM results showed excellent agreement with one another, revealing that a large variation in stresses along the AA/STI boundary was induced by the intrinsic tensile stress of the SiO2 film.

미세 표면 구조물을 갖는 패드의 제작 및 STI CMP 특성 연구

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials. There are many elements such as slurry, polishing pad, process parameters and conditioning in CMP process. Especially, polishing pad is considered as one of the most important consumables because this affects its performances such as WIWNU(within wafer non-uniformity) and MRR(material removal rate). In polishing pad, grooves and pores on its surface affect distribution of slurry, flow and profile of MRR on wafer. A subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure(MS) pad. MS pad is designed to have uniform structure on its surface and manufactured by micro-molding technology. And then STI CMP performances such as pattern selectivity, erosion and comer rounding are evaluated.

The evolution of the ion implantation damage in device processing

In this article the phenomenology related to the mechanisms of defect generation in Shallow Trench Isolation (STI) processes is discussed, and the role of the structure pattern is investigated. Defect formation is studied by plan and cross TEM analyses of wafers with different boron doses and after annealing at various temperatures. In addition, to obtain a wider statistics our analysis was extended by electrical measurements of defect-sensitive structures. It is shown that a modification of the STI flow suppresses the main mechanism of mechanical stress accumulation, hence stress-induced defects are eliminated. However, this approach is found to be critical from the point of view of the implantation damage recovery, specifically for what concerns the implantations carried out before the trench etch. This result can be explained by the role of the silicon surface in reducing the point defect excess generated in the implantation. As a consequence, in this example the presence of the STI structure is beneficial, in that it assists in annealing implantation-related defects. An attempt is also presented to model the evolution of implantation-induced defects by a Kinetic Monte Carlo code. The calculation results are promising, though the capabilities of the model are limited by the computation time.

Additional stress-induced band gap narrowing in a silicon die

Semiconductor devices have intrinsic mechanical stress due to two separate sources, silicon wafer processing and packaging. This intrinsic stress induces band gap narrowing and consequent degradation of device reliability. In this work, a silicon die that included shallow trench isolation structures was used with additional external compression to clarify the interaction effects on band gap narrowing between stresses induced by different factors. It was observed that the pressure coefficient due to the additional external compression is linearly dependent on the intrinsic tensile region/total region ratio of a p-n diode.

Thick-Strained-Si/SiGe CMOS Technology With Selective-Epitaxial-Si Shallow-Trench Isolation

We developed a new bulk strained Si/SiGe CMOS technology free from any Ge-related problems, which has a 90- to 110-nm strained Si layer thicker than the limit at which misfit dislocations occur and a new shallow-trench isolation (STI) structure that has a selective-epitaxial-Si (SES) layer to cover up the SiGe trench surface. This technology has advantages in process compatibility with Si CMOS because it allows rough treatment of cap Si surface cleaning or sacrificial oxidation. The thick-strained Si exactly causes misfit dislocations at the interface of Si/SiGe, but no degradation of the internal strain was observed. The dislocation depth is deep enough to reduce the leakage current between source and drain. SES-STI has advantages in low junction leakage current and manufacturing compatibility with Si-CMOS process. The fabricated thick-strained-Si/SiGe 0.18-mum CMOS shows the same performance enhancement factor as the usual thin (< 20 nm) strained Si/SiGe. SES-STI reduced the junction leakage current by 1.5-2 decades from the conventional STI without epitaxial Si layer. Hot carrier lifetime is the same or rather longer than control Si, which means that the quality of the gate oxide on thick-strained Si is not inferior to that of control Si.

Method for determination of the displacement field in patterned nanostructures by TEM/CBED analysis of split high‐order Laue zone line profiles

A method to extract accurate information on the displacement field distribution from split high-order Laue zones lines in a convergent-beam electron diffraction pattern of nanostructures has been developed. Starting from two-dimensional many beam dynamical simulation of HOLZ patterns, we assembled a recursive procedure to reconstruct the displacement field in the investigated regions of the sample, based on the best fit of a parametrized model. This recursive procedure minimizes the differences between simulated and experimental patterns, taken in strained regions, by comparing the corresponding rocking curves of a number of high-order Laue zone reflections. Due to its sensitivity to small displacement variations along the electron beam direction, this method is able to discriminate between different models, and can be also used to map a strain field component in the specimen. We tested this method in a series of experimental convergent-beam electron diffraction patterns, taken in a shallow trench isolation structure. The method presented here is of general validity and, in principle, it can be applied to any sample where not negligible strain gradients along the beam direction are present.

Strain field reconstruction in shallow trench isolation structures by CBED and LACBED

Using a combination of the CBED and the LACBED techniques in the transmission electron microscopy (TEM), we have investigated the strain field in the silicon active region of a shallow trench isolation structure, underlying a TiSi2 layer. Starting from the analysis of the deformation in a sample, thinned for TEM analysis, we have reconstructed the displacement field, simulating the split HOLZ lines visible in the experimental CBED patterns. From the comparison between the experimental LACBED patterns, taken in a suitable sample orientation to evidence the stressors distribution in the polycrystalline silicide layer, and the corresponding dynamically simulated ones, we have reproduced the strain field in the unthinned, bulk sample.

Analysis of Nano-scale Strain Near Shallow Trench Isolation Structures by Energy-filtered Convergent Beam Electron Diffraction

Extended abstract of a paper presented at Microscopy and Microanalysis 2006 in Chicago, Illinois, USA, July 30 – August 3, 2006

Investigating the Role of Stress in SOG-filled Shallow-Trench-Isolation Structures of sub-70 nm Device

In this work, the role of stress and shrinkage during the processing of the sub-70nm shallow-trench isolation (STI) structures filled with a spin-on glass (SOG) material containing perhydro-polysilazane is discussed. The stress behavior of this material on blanket and patterned structures are compared. The different parameters for adjusting the stress and their influences on wet-etching properties and uniformity over the wafer are discussed. Finally, the effect of stress on electrical parameters is presented.

Convergent beam electron diffraction investigation of strain induced by Ti self-aligned silicides in shallow trench Si isolation structures

The deformation induced onto silicon by the formation of Ti self-aligned silicides (salicides) in shallow trench isolation structures has been investigated by the convergent beam electron diffraction technique (CBED) in the transmission electron microscope (TEM). The splitting of the high order Laue zone (HOLZ) lines in the CBED patterns taken in TEM cross sections close to the salicide/silicon interface has been explained assuming that the salicide grains induce a local bending of the lattice planes of the underlying matrix. This bending, which affects in opposite sense the silicon areas below adjacent grains, decreases with the distance from the interface, eventually vanishing at a depth of 300–400nm. The proposed strain field has been implemented into a fully dynamical simulation of the CBED patterns and has proved to be able to reproduce both the asymmetry of the HOLZ line splitting and the associated subsidiary fringes. This model is confirmed by the shift of a Bragg contour observed in large angle CBED patterns, taken in a cross section cut along a perpendicular direction. The whole experimental results cannot be explained by just a strain relaxation of the TEM cross section, induced by the salicide film onto the underlying silicon.

Using Quantitative TEM Analysis of Implant Damage to Study Surface Recombination Velocity in Silicon

AbstractSilicon wafers with shallow trench isolation structures 3700Å deep were self-implanted with silicon at 40keV, and a dose of 1E15/cm2. This produced an amorphous layer 1000Å deep. The samples were subsequently annealed at temperatures ranging from 750°C to 900°C. The excess interstitials can recombine at the “surface” created by the proximity to the trench sidewall. Plan-view TEM was used to quantify the dislocation distribution as a function of distance from the trench sidewall. It was found that there was no measurable change in defect density as a function of distance from the trench. This was true for both the 20 minute isochronal anneal, and the isothermal study 750°C. This suggests there is a relatively weak recombination of interstitials at the surface. This is surprising given most of the TCAD models assume a very fast surface recombination velocity.

Role of Amino-Acid Adsorption on Silica and Silicon Nitride Surfaces during STI CMP

Selectivity (oxide/nitride polish rate) is a critical factor during chemical mechanical polishing (CMP) of shallow trench isolation (STI) structure, and it can be modified by adding amino acids to the slurry. The role of adsorption of the amino acids L-proline and L-arginine, on silicon dioxide and silicon nitride surfaces was characterized as a function of pH and concentration using thermogravimetric analysis. The results suggest that the adsorption behavior does not correlate with the polishing behavior of STI CMP and hence it may not play a key role in changing the selectivity.

The effect of CeO 2 abrasive size on dishing and step height reduction of silicon oxide film in STI–CMP

The effect of the CeO 2 abrasive size during chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures was investigated, in order to minimize the amount of oxide dishing and to improve the planarization efficiency. Three slurry samples were prepared based on a 1.0 wt.% abrasive concentration with different sizes of ceria particles. The step height and dishing reduction were investigated as a function of the polishing time with pattern wafers in prepared slurries. The reduction in thickness as a function of the polishing time varied between the different slurries. The dependence of the step height reduction of the patterned wafer on the polishing time showed non-linear behavior in all of the tested slurries. The amount of dishing also varied with the type of slurry. The changes in the cross-sectional profiles of the oxide as a function of the polishing time were analyzed, in order to establish a dishing and step height reduction model depending on the abrasive size. The step height variation and dishing were varied with the size of the abrasive. The observed results were explained by the contribution of inactive particles, which depended on relative size of the abrasives and the height of the remaining oxide layer.

SCR Device Fabricated With Dummy-Gate Structure to Improve Turn-On Speed for Effective ESD Protection in CMOS Technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.