Thick-Strained-Si/SiGe CMOS Technology With Selective-Epitaxial-Si Shallow-Trench Isolation

Abstract

We developed a new bulk strained Si/SiGe CMOS technology free from any Ge-related problems, which has a 90- to 110-nm strained Si layer thicker than the limit at which misfit dislocations occur and a new shallow-trench isolation (STI) structure that has a selective-epitaxial-Si (SES) layer to cover up the SiGe trench surface. This technology has advantages in process compatibility with Si CMOS because it allows rough treatment of cap Si surface cleaning or sacrificial oxidation. The thick-strained Si exactly causes misfit dislocations at the interface of Si/SiGe, but no degradation of the internal strain was observed. The dislocation depth is deep enough to reduce the leakage current between source and drain. SES-STI has advantages in low junction leakage current and manufacturing compatibility with Si-CMOS process. The fabricated thick-strained-Si/SiGe 0.18-mum CMOS shows the same performance enhancement factor as the usual thin (< 20 nm) strained Si/SiGe. SES-STI reduced the junction leakage current by 1.5-2 decades from the conventional STI without epitaxial Si layer. Hot carrier lifetime is the same or rather longer than control Si, which means that the quality of the gate oxide on thick-strained Si is not inferior to that of control Si.