Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

Abstract

Shallow trench isolation (STI) is the predominating isolation technology for advanced integrated circuits, but the oxide thickness of the convex corner of trenched Si surfaces is thinner than other planar Si surfaces, which causes leakage currents and gate oxide reliability degradation of electrically erasable and programmable read only memory (EEPROM) by the keen convex corner region. We present an improved shallow trench isolation process to reduce leakage currents by sacrificial thermal oxide, liner silicon nitride, and Low Pressure Chemical Vapor Deposition Medium Temperature Oxide (LPCVD MTO). We found that the sample fabricated by an improved STI process with sacrificial oxidation of EEPROM decreased leakage currents and eliminated humps shown at the samples fabricated by conventional STI process, and also obtained more improved endurance characteristics stress biases applied at wordlines. In spite of the shortcoming that it provides a few additional shallow trench isolation process steps, it is an effective method to reduce oxide leakage currents and alleviate oxide reliability degradation.