Shallow Trench Isolation Stress Research Articles

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs

In this paper, we study the impact of through-silicon-via (TSV) and shallow trench isolation (STI) stress on the timing variations of 3-D IC. We also propose the first systematic TSV-STI-stress-aware timing analysis and show how to optimize layouts for better performance. First, we generate a stress contour map with an analytical radial stress model for TSV. We also develop a stress model for STI from finite element analysis results. Then, depending on geometric relation between TSVs, STI, and transistors, the tensile and compressive stresses are converted to hole and electron mobility variations. Mobility-variation-aware cell library and netlist are generated and incorporated into an industrial engine for timing analysis of 3-D IC. We observe that TSV stress and STI stress interact with each other, and rise and fall time react differently to stress and relative locations with respect to both TSVs and STIs. Overall, TSV-STI-stress-induced timing variations can be as much as ±15% at the cell level. Thus, as an application to layout optimization, we exploit the stress-induced mobility enhancement to improve performance of 3-D ICs. We show that stress-aware layout perturbation could reduce cell delay by up to 23.37% and critical path delay by 6.67% in our test case.

A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Strain technology has become indispensable for present CMOS integrated circuits (ICs) as the feature size of transistor shrinks. In the meantime, stress-induced variation has also become an unavoidable problem. Unintentional stress, such as shallow trench isolation (STI)- induced stress, is one of the main variation sources and is strongly layout dependent. In this paper, a new 2-D layout-dependent STI stress model and related device parameter model are proposed. The stress model captures layout parameters along both the longitudinal direction and the transverse direction, based on which channel stress induced by STI is derived. Device parameters including threshold voltage, mobility, and saturation velocity are then modified according to several analytical models. The model can be integrated into standard CMOS IC design flow. By comparing with TCAD simulation and experiments with 65-nm process, it shows that the new model can give a better prediction accuracy than the original process design kit.

A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization

With the continuous shrinking of the feature size, the effect of stress on the performance of the IC device and circuit can no longer be ignored. In fact, stress engineering is becoming more and more widely used today in advanced IC manufacture processes to improve device performance. Different from the intentionally introduced stresses to improve circuit performance, the shallow-trench-isolation (STI) stress, which is exerted by STI wells on the active area of devices, is a by-product of the fabrication process and has increasingly significant impact on the circuit behavior. This paper proposes a complete flow to characterize the influence of STI stress on the performance of RF/analog circuits by considering detailed layout and process information. An accurate and efficient finite-element method-based stress simulator has been developed to extract stress distribution from layouts of IC designs. The existing MOSFET model is also enhanced to capture the effects of stress on mobility, threshold voltage. With the enhanced model, we are able to study the influence of layout-dependent STI stress on the performance of real circuits and establish corresponding optimization strategies. The proposed flow has been applied to a series of RF/analog IC designs based on a 90-nm CMOS technology.

A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> and effective mobility μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cf</i> (poly-end), respectively. Both categories of parasitic capacitance lead to overestimated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> and underestimated μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> . The increase in effective channel width <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> due to Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> from shallow trench isolation (STI) top-corner rounding may compensate μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> degradation due to STI stress. The tradeoff between μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> determines the impact of width scaling on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Gm</i> . A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.

Physical-Based Threshold Voltage and Mobility Models Including Shallow Trench Isolation Stress Effect on nMOSFETs

Physical-based threshold voltage and channel mobility models to include shallow trench isolation (STI) mechanical stress effects on MOSFET I-V characteristics were described. The parameter Δs, meaning the change along the MOSFET channel length under STI stress, ΔEeceg , ΔEdos, and ΔEm, meaning the activation energy per strain due to STI stress are used in models. ΔEeceg describes the STI-stress-induced electron affinity, band-gap narrowing effects. ΔEdos describes density-of-states changes due to the light and heavy hole mass changes under STI stress, and ΔEm corresponds to the STI-stress-induced mobility changes. The STI stress induced tens of millivolts shifts in threshold voltage, and 40% shift in channel mobility on nano-MOSFET region. The models are verified by the 130-nm technology nMOSFET-layout-dependent experiment data including various gate length, active area, and gate location.

A physical-based pMOSFETs threshold voltage model including the STI stress effect

The physical threshold voltage model of pMOSFETs under shallow trench isolation (STI) stress has been developed. The model is verified by 130 nm technology layout dependent measurement data. The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET. The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11% improvement of average delay time. This indicates the importance of STI stress consideration in circuit design.

NMOS Narrow Width Devices Drive Current Improvements through STI Processes and Channel Implantation Optimization

NMOS narrow width transistor driving current as a function of shallow trench isolation (STI) processes and channel implant conditions were studied on a 65nm CMOS technology. It is found that the magnitude of compressive stress in STI could modulate the trend of NMOS drive current versus width dependence that was attributed to channel dose profile uneven distribution under the influence of stress. It is seen that the channel body effect factor (gamma) of large width (W=10um) transistor is smaller than that of narrow width device (W=0.12um). This difference increases as STI compressive stress scales up. The phenomena are consistent with the analysis that Boron dose distribution varies as STI stress changes. it is shown that the down trend of drive current for narrow width transistors could be minimized by STI process optimization, or by introducing indium implantation during channel implantation processes.

The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs

The impact of channel width scaling on low-frequency noise (LFN) and high-frequency performance in multifinger MOSFETs is reported in this paper. The compressive stress from shallow trench isolation (STI) cannot explain the lower LFN in extremely narrow devices. STI top corner rounding (TCR)-induced ΔW is identified as an important factor that is responsible for the increase in transconductance Gm and the reduction in LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate the effective mobility (μeff) degradation from STI stress and the increase in effective width (Weff) from ΔW due to STI TCR. The proposed model can accurately predict width scaling effect on Gm based on a tradeoff between μeff and Weff. The enhanced STI stress may lead to an increase in interface traps density (Nit), but the influence is relatively minor and can be compensated by the Weff effect. Unfortunately, the extremely narrow devices suffer fT degradation due to an increase in Cgg. The investigation of impact from width scaling on μeff, Gm, and LFN, as well as the tradeoff between LFN and high-frequency performance, provides an important layout guideline for analog and RF circuit design.

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Ultrathin DPN STI SiON liner for 40nm low-power CMOS technology

At sub-40 nm CMOS technology nodes, the implementation of shallow trench isolation (STI) becomes more challenging due to shrinking geometries and stricter device leakage requirements. As device geometries are shrinking, STI liner is also becoming thinner and plays an important role for the minimal consumption of device active area while effectively rounding the STI corner and minimizing stress-induced defects. Consequently, STI stress is enhanced by the scaling of STI-pitch, the volume expansion induced by STI liner and film stress of filling materials. This paper discusses the benefits of SiON liner growth by decoupled-plasma-nitridation (DPN) and SiON liner induced stress compared to conventional pure oxide liner growth by in situ steam generation (ISSG). Thin STI SiON liner offers lower sub-threshold leakage current without drive current loss for transistor performance. Moreover, junction leakage current is also reduced with scaling device active area. Thus, better device performance results in better minimum operation voltage (Vcc_min) of low-power 6T-SRAM. This paper demonstrates the influences of thin STI SiON liner growth by DPN in STI manufacture.

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns

Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.

Shallow Trench Isolation Stress Effect on NMOS Transistor Leakage, SRAM Standby Current and VCCMIN

Three key process steps in shallow trench isolation (STI) technology: STI liner oxide, STI to AA step height, and annealing temperature. Their impacts on NMOS devices leakage, SRAM standby current and Vccmin have been studied. MOSFET transistors off state current (Ioff) and body current (IB) were measured at varied length of diffusion (LOD) for STI stress effect analysis. For low power NMOSFET transistors, IB is seen to be the main part of Ioff and has a strong correlation to the processes that modulates STI stress. The experiment results show that the STI stress level can be much reduced by decreasing STI oxide RTA temperature and liner ox thickness, hence leading to lower IB and SRAM standby current. It is also demonstrated that SRAM Vccmin can be improved ~10% by STI stress reduction.

The Impact of Shallow Trench Isolation on the Channel Hot Electron Programming Behaviors of SONOS Cells

As scaling down of the flash memory cell size continues, the impact of shallow trench isolation(STI) on active area(AA) in cell array becomes much more severe. Two types of influence have been reported: i) boron segregation: boron atoms at AA corner around STI tend to diffuse out, which induces lower boron concentration at AA corners; ii) STI stress: a compressive stress, coming from STI. The former may cause lower threshold voltage of edge cells. The latter will reduce the electron mobility, leading to higher threshold voltage for n-channel cells. In this work, we have studied the impact of STI on the channel hot electron programming behaviors of SONOS cells on single cell and array level. It has been found that the programmability of cells adjacent to STI is different from that of center cells. Boron segregation will substantially decrease the program efficiency while the stress will increase the initial programming voltage. In this paper, the impact of STI on edge cells will be reported and compared with the simulation results.

Effect of STI stress on leakage and Vccmin of a sub-65 nm node low-power SRAM

In the paper, for the first time, the effects of shallow trench isolation (STI) stress enhanced boron diffusion on band-to-band (BTBT) leakage and Vccmin of a 65 nm node low-power SRAM are investigated in detail. High temperature oxidation in the STI process induces an elastic stress to enhance the diffusion of boron dopants, thus leading to a significant increase in BTBT on the STI edge sidewall. The enhanced boron diffusion is more serious for a shorter and/or narrower device, thus worsening the mismatch of the threshold voltage and Vccmin of the devices in a 65 nm node SRAM cell significantly.

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress

A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, (110) and (100), both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to ∼20% and ∼50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

STI-to-gate distance effects on flicker noise characteristics in 0.13 μm CMOS

The geometry effect on the flicker noise characteristics and the variations in 0.13μm CMOS transistors were studied. By symmetrically extending the distance between the shallow-trench-isolation (STI) to the gate, both NMOS and PMOS presented obvious improvement on the noise characteristics. As the distance increased from 0.6μm to 10μm, the average noise level reduced by more than one order of magnitude (NMOS) and the standard deviations σdB improved from 5.95dB to 1.79dB for NMOS and from 3.93dB to 2.17dB for PMOS, respectively. To further identify the noise mechanism, the devices with asymmetrical STI-to-gate distances were also investigated. It was found that the distance in the source side (SA) has a much higher impact on the observed noise characteristics. The results suggested that the noise characteristics were dominated by the STI stress induced traps for both NMOS and PMOS studied here. In addition, the carrier number fluctuation model with the correlated mobility scattering could be more suitable to describe the noise characteristics in these devices.

Combining a Novel Charge-Based Capacitance Measurement (CBCM) Technique and Split $C$–$V$ Method to Specifically Characterize the STI Stress Effect Along the Width Direction of MOSFET Devices

The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, the effect along the width direction has seldom been specifically analyzed. In this paper, we combine a novel charge-based capacitance measurement technique, which is used to extract the intrinsic of MOSFET devices, and the split capacitance-voltage method to extract the mobility of devices with various channel widths. Although it is already known that under the influence of compressive STI stress along the width direction the mobility of both NMOS and PMOS devices will degrade with decreasing width, it is the first time to quantify the impact of this STI stress component on MOSFET devices.

Channel Strain in Advanced Complementary Metal–Oxide–Semiconductor Field Effect Transistors Measured Using Nano-Beam Electron Diffraction

Using high-precision nano-beam electron diffraction (NBD), we clarified the influences of stress liner and the stress of shallow trench isolation on channel strain in advanced metal–oxide–semiconductor field effect transistors (MOSFETs). For systematic strain measurements, we improved the precision of NBD by observing large reciprocal lattice vectors under appropriate diffraction conditions. The absolute value of the channel strain increases by stress liner as gate length decreases, although the drive current increase due to stress liner saturates at a shorter channel length. The normal strain in the gate length direction is inversely proportional to the distance from the gate electrode to the shallow trench isolation (STI). Furthermore, the relationship between measured channel strain induced by STI and drive current change was shown. The drive current of n- and p-MOSFET changes about 5% with 2×10-3 channel strain variation. This result suggests that reducing the shallow trench isolation stress is effective for controlling the drive current change, depending on the active region layout. We conclude that the experimental measurement of channel strain is necessary for device and circuit design.

Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.

Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches

The interactions of shallow trench isolation (STI) stress and various mobility enhancement approaches in silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) have been systematically studied. Strong interactions between STI stress and contact etch stop layer (CESL) stress on channel mobility were observed which was attributed to the amplification of CESL channel tensile stress with length of diffusion (LOD) reduction. In this work, an almost completely reversed P-channel metal oxide semiconductor field-effect transistor (PMOSFET) mobility-LOD trend in both <110 >/(100) and <100 >/(100) oriented SOI wafers was found, which is caused by the reversed polarity of piezoresistance coefficients. On the other hand, charge pumping leakage was enhanced by the post-gate oxide stress (CESL stress) only, and was not affected by any stress applied prior to the gate oxidation step (STI stress).