NMOS Narrow Width Devices Drive Current Improvements through STI Processes and Channel Implantation Optimization

Abstract

NMOS narrow width transistor driving current as a function of shallow trench isolation (STI) processes and channel implant conditions were studied on a 65nm CMOS technology. It is found that the magnitude of compressive stress in STI could modulate the trend of NMOS drive current versus width dependence that was attributed to channel dose profile uneven distribution under the influence of stress. It is seen that the channel body effect factor (gamma) of large width (W=10um) transistor is smaller than that of narrow width device (W=0.12um). This difference increases as STI compressive stress scales up. The phenomena are consistent with the analysis that Boron dose distribution varies as STI stress changes. it is shown that the down trend of drive current for narrow width transistors could be minimized by STI process optimization, or by introducing indium implantation during channel implantation processes.