<title>Defect detection strategies for chemical-mechanical polishing process in shallow-trench isolation applications</title>

Abstract

Shallow trench isolation (STI) process has become an architectural requirement for sub 0.25 micron device rules, as localized oxidation of silicon (LOCOS) does not deliver the benefits from smaller design rule. The challenge of STI is not only typically to planarize a high-density plasma oxide and SiN using CMP (Chemical Mechanical polish) process in the same time, but also to reduce STI process associated defects, which could cause yield loss and reliability issues. In a typical CMOS fabrication flow, STI module is usually the very first process module in the whole process. Therefore, detect, characterize, and reduce the STI CMP related defect is very important. Because it is not only to improve yield and reliability, but also to reduce the background noise in defect monitoring for the rest of the front-end processes lines. A methodology for in-line STI defect identification, reduction using KLA array mode and AIT with RMBT, has been developed for yield enhancement at VLSI/Philips. This paper also details the implementation of in-line defect inspection in STI process module. STI CMP process parameters related to the defects have been investigated to improve yield and reliability.