Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Abstract

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.