Sense Margin Research Articles

VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting

Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelectronics 65-nm technology show that the proposed sensing circuit achieves 807-mV worst case sense margin on average, read access pass yield of $14.4\sigma $ in typical corner and $4.7\times $ reduction in read power compared to conventional voltage sensing.

Design Space Exploration for Selector Diode-STTRAM Crossbar Arrays

We report a simulation-based study to understand the integration potential of selector diode (SD) with spin-transfer torque random access memory (STTRAM). SD based on metal–insulator–insulator–metal diode is considered due to features such as high-speed operation, ability to engineer dielectric interfaces and electrode barriers for low $V_{T}$ and bidirectional switching, and immunity to the temperature (due to its tunnel-based conduction). The intended asymmetry in diode $I$ – $V$ behavior provides better sense margin for larger arrays. We describe design challenges and propose device-circuit co-optimization and novel techniques, e.g., write voltage biasing and series/parallel connected SD for robustness and retention. This is the first effort toward solving the design challenges to enable diode-STTRAM crossbar. The proposed structure can enable 3-D stacking of magnetic tunnel junction for densities beyond 4F2.

Reading Nanomagnetic Energy Minimizing Coprocessor

Nanomagnetic coprocessor enacts an energy minimization framework to solve the quadratic optimization problem often arisen in a computer vision paradigm. Our approach relies on the fact that the Hamiltonian of a system of coupled nanomagnets is quadratic. Therefore, a wide class of quadratic energy minimization can be solved directly by the relaxation physics of a grid of nanomagnets. The solutions of such problems are obtained from reading the magnetic state of the cells, in other words, the resistance. This monograph explores the methods to detect the magnetic states, and also considers the dimensional variation of each cell of the coprocessor and inspects the resultant change in resistance. We measure at most ${\text{7.8}}$ % change in resistance due to the process imperfection of in-house fabrication processes. This requires a read circuitry that can handle the largest deviation. Unlike STT-MRAM, the circular magnets do not have shape anisotropy but, here we show that with an additional preamplifier circuit, we are able to improve sense margin by at least ${\text{73}}$ %.

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ∼1.2 μA μm−1 along with a longer retention time (RT) of ∼1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell

Content Addressable Memory (CAM) is widely used in applications where searching a specific pattern of data is a major operation. Conventional CAMs suffer from area, power, and speed limitations. We propose Spin-Torque Transfer RAM--based Ternary CAM (TCAM) cells. The proposed NOR-type TCAM cell has a 62.5% (33%) reduction in number of transistor compared to conventional CMOS TCAMs (spintronic TCAMs). We analyzed the sense margin of the proposed TCAM with respect to 16-, 32-, 64-, 128-, and 256-bit word sizes in 22nm predictive technology. Simulations indicated a reliable sense margin of 50mV even at 0.7V supply voltage for 256-bits word. We also explored a selective threshold voltage modulation of transistors to improve the sense margin and tolerate process and voltage variations. The worst-case search latency and sense margin of 256-bit TCAM is found to be 263ps and 220mV, respectively, at 1V supply voltage. The average search power consumed is 13mW, and the search energy is 4.7fJ/bit search. The write time is 4ns, and the write energy is 0.69pJ/bit. We leverage the NOR-type TCAM design to realize a 9T-2 Magnetic Tunnel Junctions NAND-type TCAM cell that has 43.75% less number of transistors than the conventional CMOS TCAM cell. A NAND-type cell can support up to 64-bit words with a maximum sense margin of up to 33mV. We compare the performance metrics of NOR- and NAND-type TCAM cells with other TCAMs in the literature.

Ultra-low power 1T-DRAM in FDSOI technology

A systematic study of a capacitorless 1T-DRAM fabricated in 28nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z2-FET memory cell features a large current sense margin and small OFF-state current at 25°C and 85°C. Moreover, low power consumption during state ‘1’ writing is achieved with ~0.5V programming voltage. These specifications make the Z2-FET an outstanding candidate for low-power eDRAM applications.

Survey of STT-MRAM Cell Design Strategies

Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed in this article. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, sense margin, and energy or power consumption costs versus resiliency benefits. Solutions to the reliability issues identified are addressed within a taxonomy created to categorize the current and future approaches to reliable STT-MRAM designs. A variety of destructive and non-destructive sensing schemes are assessed for process variation tolerance, read disturbance reduction, sense margin, and write polarization asymmetry compensation. The highest resiliency strategies deliver a sensing margin above 300mV while incurring low power and energy consumption on the order of picojoules and microwatts, respectively, and attaining read sense latency of a few nanoseconds down to hundreds of picoseconds for non-destructive and destructive sensing schemes, respectively.

A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by $2\times $ and reduces the write energy by $3\times $ compared with the 2T 2MTJ cell and by $1.5\times $ compared with the 1T 1MTJ cell.

Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory

Magnetoresistive random access memory (MRAM) suffers from low magnetoresistance ratio and serious variations in both low-resistance state (R P ) and high-resistance state (R AP ). The resulting narrow resistance window between R P and R AP makes it difficult to acquire a sufficient sense margin for accurate read operation. In this brief, a novel read circuit for MRAM is proposed with dynamic data-dependent reference current to improve the sense margin. Instead of using the average of read currents of a pair of dummy R P and R AP cells as reference, our reference current is generated in a data-dependent manner by subtracting the read current of the selected cell from the sum of read currents of a pair of dummy R P and R AP cells. Thus, a larger or smaller reference current can be obtained for the read of R AP or R P cell, respectively, helping in expanding the sense margins. The larger sense margin can further improve the sense speed and the read yield. Evaluation shows that 2× increase in typical sense margin, 60% reduction in sense time, and remarkable reduction in bit error rate are achieved compared with the conventional averaging reference scheme. The accompanying cost in power consumption is acceptable.

Analysis of Functional Oxide based Selectors for Cross-Point Memories

We present an extensive analysis of functional-oxide based selector devices for cross-point memories from the perspectives of materials through arrays. We describe the design constraints required for proper functionality of a cross-point array and translate these constraints to figures of merit for the selector materials. The proposed figures of merit, related to the resistivities of the functional oxide in the metallic and insulating states and the critical current densities for insulator-metal transitions, determine whether or not a functional oxide is suitable to be employed as a selector for a memory technology. Our analysis shows the importance of co-optimizing the selector length with the read/write voltages and establishes the range of these parameters for proper functionality. We also perform an extensive material space analysis for the selector, relating the selector properties to the achievable array metrics. For instance, we show that optimized memory array with single crystal VO $_{\mathrm {{2}}}$ based selector and spin-memory element achieves $\sim 25\mu \text {A}$ sense margin with ~ 30% read disturb margin and 40ns write time. The leakage in the half-accessed cell can be as low as $15\mu \text {W}$ . The design principles established in this work will provide guidelines for future exploration of functional oxides for selector applications as well as for the optimization of cross-point arrays.

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current ( $I_{W}$ ), on / off -state resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}}$ / $R_{{\mathrm{\scriptscriptstyle OFF}}}$ ), and $I$ – $V$ nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high $R_{{\mathrm{\scriptscriptstyle ON}}}$ ) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With $R_{{\mathrm{\scriptscriptstyle ON}}}=500~\text{k}\Omega $ ( $I_{W}=6~\mu \text{A}$ ) and nonlinearity ratio $=10$ , 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with $\sim 2$ -pJ/bit energy consumption.

High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Benefiting from its simple switching scheme (only a bidirectional current source), high-speed and low-power spin-transfer torque (STT) has been regarded as one of the most promising switching mechanisms for a magnetic tunnel junction (MTJ)-based non-volatile memory and logic circuits. However, it suffers from a number of reliability issues like write error induced by its intrinsic stochasticity, process variation, and so on. In order to reduce the write error rate, the mainstream solution is to enlarge the write pulse duration at the expense of write energy dissipation. Some self-terminated write circuits have been proposed to avoid the wasted write energy. But the hardware cost of these write circuits is especially large. In this paper, a novel cost-efficient self-terminated write circuit is proposed using two simple built-in sensing circuits. The proposed write circuit is simulated with a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit. The simulation result shows about 35% reduction of circuit area and 10% lower energy consumption in comparison with that in prior work. In addition, the Error-Free write operation under process variation of both the CMOS transistor and the STT-MTJ is achieved due to its large sense margin ( $\sim 320$ mV).

Performance optimization of 1T-1C DRAMs: A quantitative study

There is no doubt that the one-transistor one-capacitor dynamic random-access memories (1T-1C DRAMs) play the most important role as the main memory in several volatile storage systems. The performance of this type of memories is dependent to a large extent on the size of the cell-storage capacitor, Cs, the bitline-parasitic capacitance, CBL, and the bitline precharge level, Vpre. In this paper, the performance of such memories will be evaluated by a proposed figure of merit (FOM) that takes into account the area, the sense margin, the average power consumption, and the average cycle time in the entire memory chip. A quantitative analysis will be performed in order to derive a compact form for the proposed figure of merit. This figure of merit will be evaluated for a certain technology and for certain ranges of Vpre, Cs, and CBL with the optimum values of these parameters determined. The impact of technology scaling on the performance of the 1T-1C DRAM will also be investigated. The derived expressions for the read-access time and the power consumption will be compared with the simulation results for the 45nm CMOS technology with VDD=1V.

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large $R_{\mathrm{{\scriptscriptstyle OFF}}}$ / $R_{\mathrm{{\scriptscriptstyle ON}}}$ , 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic $RC$ mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of $2.5\times $ typical $R_{\mathrm{{\scriptscriptstyle ON}}}$ or $R_{\mathrm{{\scriptscriptstyle OFF}}}$ in reliability are achieved for proposed nvLUT with six inputs.

Novel Self-Reference Sense Amplifier for Spin-Transfer-Torque Magneto-Resistive Random Access Memory

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard 0.18 mm CMOS process. The proposed selfreference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic

A cost-efficient self-terminated write driver is proposed for low-energy RAM and logic circuits by using spin-transfer-torque (STT)-magnetic tunnel junction (MTJ) devices. Since a bidirectional write current is required for STT switching, data-dependent write-completion monitoring, where the node with large voltage difference between before and after the switching is selectively used, makes it possible to achieve sufficiently large sense margin at any write current directions. By the enhancement of sense margin, write-completion monitoring and self-write-termination circuitries are simplified. Thus, 60% of transistor counts reduction and further robust write-completion detection under process variation are achieved in comparison with those of the prior work.

Physical insights of body effect and charge degradation in floating-body DRAMs

Floating Body one transistor Dynamic Random Access Memories (FBRAMs) have been widely studied and proposed in the literature as an alternative for conventional one transistor/one capacitor DRAMs. FBRAM performance depends on charge degradation during READ and HOLD operations and on the body effect during READ operation, the first setting the amount of the residual non-equilibrium charge during READ operation, and the second setting the effectiveness of this residual charge to modulate the source-body barrier during READ operation. In this work it is proposed a simple analytical charge-based compact model for the body-effect in FBRAMs which is able to reproduce device performance in terms of READ Sense Margin and current ratio. Physical insights of the body effect and charge degradation mechanisms, with particular emphasis to their bias dependence, are discussed in detail. Conclusions can be useful for the choice and the optimization of the bias in FBRAMs. All the discussion is supported by two-dimensional drift–diffusion device simulation on a template double-gate MOSFET.

2T–1R STT-MRAM memory cells for enhanced on/off current ratio

Novel spin torque transfer magnetic tunnel junction (STT-MTJ) based memory cell topologies are introduced to improve both the sense margin and the current ratio observed by the sense circuitry. These circuits utilize an additional transistor per cell in either a diode connected or gate connected manner and maintain leakage current immunity within the data array. An order of magnitude increase in the current ratio over a traditional 1T–1R structure is observed. This improvement comes at a cost of 61% and 117% increase in area, respectively, for the diode and gate connected cells.

Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM

This paper investigates the front and back gate bias influence on current sense margin and retention time in Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices used as a FBRAM (floating body random access memory) cell through simulations and experimental results. This work aims to gain insight into the mechanisms involved into FBRAM operation and optimize the front and back gate biases for achieving the best retention time and current sense margin.The writing ‘1’, through BJT effect, and writing ‘0’, by using capacitive coupling, were verified. We demonstrated that, during the holding, the operation mode of the interfaces is an important factor for the best condition for achieving both a higher current sense margin and a longer retention time, which should be with the front gate in accumulation mode and the back gate in depletion mode.It was also observed that depending on gate bias applied during the hold operation, there are two mechanisms involved in retention time. For less negative gate voltage the retention time is limited by recombination, whereas for more negative gate voltage the generation mechanisms take place.Moreover, the retention time showed more sensitivity to the back gate voltage than the current sense margin.