Abstract
Novel spin torque transfer magnetic tunnel junction (STT-MTJ) based memory cell topologies are introduced to improve both the sense margin and the current ratio observed by the sense circuitry. These circuits utilize an additional transistor per cell in either a diode connected or gate connected manner and maintain leakage current immunity within the data array. An order of magnitude increase in the current ratio over a traditional 1T–1R structure is observed. This improvement comes at a cost of 61% and 117% increase in area, respectively, for the diode and gate connected cells.
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