Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Abstract

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large $R_{\mathrm{{\scriptscriptstyle OFF}}}$ / $R_{\mathrm{{\scriptscriptstyle ON}}}$ , 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic $RC$ mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of $2.5\times $ typical $R_{\mathrm{{\scriptscriptstyle ON}}}$ or $R_{\mathrm{{\scriptscriptstyle OFF}}}$ in reliability are achieved for proposed nvLUT with six inputs.