Sense Margin Research Articles

High performance Si-MoS2 heterogeneous embedded DRAM.

Embedded Dynamic RAM (eDRAM) has become a key solution for large-capacity cache in high-performance processors. A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS2) is reported to address the short retention issue in conventional gain cell (GC) eDRAMs meanwhile eliminate the pillar capacitor in one transistor and one capacitor (1T1C) eDRAMs. The MoS2 write transistor with low OFF current (IOFF) enables long data retention, while the Si read transistor offers high drive current and logic compatibility. This combination enhances data retention by 1000 times and sense margin by 100 times respectively compared to full Si and MoS2 counterparts. A three-dimensional (3D) design stacking MoS2 on Si is demonstrated with back-end-of-line (BEOL) process to double integration density. With 6000 s data retention, 35 μA/μm sense margin, 5 ns access speeds, 3D integration and CMOS logic compatibility, this Si-MoS2 eDRAM marks a significant advancement in memory technology.

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

A Low-Power BL Path Design for NAND Flash Based on an Existing NAND Interface

This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access time with a scaled CMOS in IOs. The power supply for IO buffers, namely, VDDQ, decreases from 3 V to 1.2 V, accordingly. In this paper, the way in which a reduction in VDDQ can contribute to power reduction in the BL path is discussed and validated. Conventionally, a BL voltage of about 0.5 V has been supplied from a supply voltage source (VDD) of 3 V. The BL path power can be reduced by a factor of VDDQ to VDD when the BL voltage is supplied by VDDQ. To maintain a sense margin at the sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and an equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in the BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in the die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison to the significant power reduction in the BL path power of the NAND die of about 60%. The BL path is then designed in 180 nm CMOS to validate the design. When the cost for powering the SSD becomes quite significant, especially for data centers, an additional lower voltage supply, such as 0.8 V, dedicated to BL charging for read and program verifying operations may be the best option for future applications.

Data-cell-variation-tolerant triple sampling non-destructive self-reference sensing scheme of STT-MRAM

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

A novel read circuit for RRAM based on RC delay effect

AbstractIn this paper, a novel Resistive Random‐Access Memory (RRAM) read circuit has been designed and verified by simulation based on the RRAM model and parasitic capacitance of the circuit. Simulation results demonstrate the feasibility and effectiveness of the proposed circuit, with accurate reading of RRAM states and fast reading speed in the nanosecond range. The sense margin of the proposed circuit has improved as the array size increases, enhancing its application for advanced node RRAM array manufacture. Compared with conventional circuits, the proposed circuit achieved power consumption reduction of 6% and area reduction of 46.9 um2, resulting in a 97.5% reduction in area, providing an effective solution to address the cost and chip size challenges associated with RRAM industrialization.

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance

This brief proposes a compact spin-orbit torque magnetic random-access memory (SOT-MRAM) cell structure with high read performance for embedded nonvolatile memory (eNVM) applications. The memory cell is composed of one transistor, two Schottky diodes, two magnetic tunnel junctions (MTJs) and one shared heavy metal (HM) layer, which can be abbreviated as 1T-2D-2MTJ cell. The two MTJs are stacked on the same HM layer for smaller area overhead and configured to be complementary with the magnetization of their pinned layers in the opposite direction to double the read sense margin. The write operation is also simplified since a current through the HM layer changes the resistances of both MTJs simultaneously. The evaluations include the micromagnetic simulation of the SOT device, the analysis of PVT variations for the read operation on bit-cell level, the estimation of bit-cell area and the simulations of performance and power consumption on array level. The results show that the proposed SOT-MRAM improves the performance and reliability of the read operation and achieves 75% (50%) reduction in bit-cell area compared to 4T-2MTJ SOT-MRAM (2T-2MTJ STT-MRAM), 83.0% reduction in write power consumption and 91.1% reduction in write latency compared to 2T-2MTJ STT-MRAM.

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+-n-p-n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10-15 J/bit for the write '1' operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1 T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (∼1 ns) and read (∼1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be a challenge for energy efficient system-on-chip applications.

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory (NVM) due to its large resistance ratio in different switching states. To improve memory density and reduce cost-per-bit, multi-level cell (MLC) RRAM stores multiple bits in a single cell, compared to a single-level cell (SLC). However, random mismatch, process variation, and resistance shift lead to reliability issues, degrade the probability of correct read, and increase the bit error rate (BER). This paper presents a time-based sensing scheme for robust read operation and extends to multi-level sensing for SLC and MLC RRAM arrays. Bit line (BL) voltage is converted into time delay by a voltage-to-time converter (VTC) and compared with the implicit timing reference generated by a delay line. By detecting different states in the time domain, the proposed time-mode sense amplifier (TSA) requires no analog reference voltage or current, which is used in the conventional voltage-mode sense amplifiers (VSA) or current-mode sense amplifiers (CSA). Power gating is employed to enable the time sampling only at the sensing points to suppress the short-circuit current. A charge sharing-induced error compensation (CSEC) circuit is used to eliminate the charge sharing-induced voltage drop and expand the sense margin by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56\times $ </tex-math></inline-formula> . Monte Carlo simulations in 40nm technology show that the proposed TSA improves read reliability and reduces BER by 3–4 orders of magnitude compared to conventional VSA and CSA. The proposed time-based sensing scheme operates from 0.7-1.2 V supply and consumes 49 fJ/bit for read operation under a nominal 1.2 V supply.

Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths

Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random access memory (VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low-power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{S}$ </tex-math></inline-formula> ) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin (SM), offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{S}$ </tex-math></inline-formula> in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically isolated but magnetically coupled PMA magnets via interlayer exchange coupling. Designing the proposed devices using object-oriented micromagnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared with the existing VSH-MRAMs, our design achieves 39%–42% and 36%–46% reduction in read time and energy, respectively, along with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1\times - 1.3\times $ </tex-math></inline-formula> larger SM at a comparable area. This comes at the cost of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.0\times $ </tex-math></inline-formula> increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes.

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Capacitorless dynamic memory (one transistor dynamic random access memory (1T-DRAM)) operation in a reconfigurable field effect transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (L UG), control gate (L CG), polarity gate (L PG), storage region length (L S), and total length (L T) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of L S/L T and L CG/L T shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed L T, retention time can vary over a wide range (550 ms to 8.7 s) depending on the values of L S/L T and L CG/L T, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing L CG/L T to ensure improved 1T-DRAM metrics in terms of enhanced retention (>64 ms), acceptable sense margin (>6 µA µm−1), current ratio (>104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line (WL)/bit line (BL) are also analysed in this work. Results indicate that state ‘0’ of the cell sharing BL with the selected cell is strongly affected by BL disturbance. WL disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

High-Speed Memristive Ternary Content Addressable Memory

This article presents an ultra-high-speed memristor-based non-volatile Ternary Content Addressable Memory (TCAM) for use in real-time and big-data applications that require low power dissipation and fast data retrieval. It proposes a novel memristive TCAM (MTCAM) cell using memristors as a bit storage device along with an ultra-fast match line sense amplifier to minimize search time. SPICE simulation on 45 nm technology show that the search delay on a 144-bit proposed MTCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ. It is 1.12× times faster and dissipates 67 percent less search energy per bit than the fastest existing 144-bit MTCAM design.

Robust transmission gate-based 10T subthreshold SRAM for internet-of-things applications

This paper presents a transmission-gate-based 10T (TG10T) subthreshold SRAM cell for internet of things applications. To estimate its relative strength, it is compared with six-transistor (6T), transmission gate (TG)-based 8T (TG8T), and fully differential 8T (FD8T) cells subjected to severe process variations. The simulation results are carried out using HSPICE software and a 16 nm CMOS technology node. The TG10T cell uses a differential scheme to enhance the sense margin, two TGs instead of two NMOS access transistors to enhance write-ability, and two extra buffer transistors to improve read stability. The proposed TG10T cell minimizes leakage power dissipation by means of a greater number of PMOS devices. The proposed cell shows at least a 1.67X lower read delay (T RA) and a 1.13X higher read static noise margin. In addition, it offers a 1.22X and 1.52X lower write delay (T WA), and a 1.36X and 1.40X higher write static noise margin (WSNM) than that of 6T and FD8T, respectively. The TG10T cell consumes 2.06X/1.28X lower dynamic/leakage power compared to the 6T cell. For all these improvements, it incurs a penalty of 1.24X T WA, 1.48X WSNM, and 1.12Xdynamic power when compared with the TG8T cell, at V DD = 0.36 V. However, when subjected to severe process variations, the proposed TG10T cell shows high reliability. Moreover, a 2 kb SRAM memory using the proposed TG10T cell along with peripheral circuitries is implemented to evaluate the proposed cell’s performance in an array level.

An Insightful Assessment of 1T-DRAM With Misaligned Polarity Gate in RFET

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ge 6~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented.

Sensitivity implications for programmable transistor based 1T-DRAM

In this letter, we report an insightful evaluation of the base performance and sensitivity of 1T-DRAM implemented through a programmable or reconfigurable transistor (RFET). Although RFET based 1T-DRAM exhibits enhanced retention time (>64 ms at 85 °C and 125 °C) with an appreciable sense margin (∼16 µA/µm) and total length scalability down to 50 nm, metrics are sensitive to biases, parameter variations and traps. RFET exhibiting highest retention is expected to offer a relatively narrow operating window (~75 mV) for read bias. This stringent criterion can be relaxed with a wider read bias window (~150 mV) in RFET architectures exhibiting retention lower than maximum but still higher than >64 ms.

Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

In this paper, a dopingless DRAM based on work function engineered Tunnel field effect transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF current ratio of drain current, thereby improving the sense margin and retention time. Drain electrode is made up of dual metal, so as to suppress ambipolar current. The analysis of dual material gate dual drain electrode DRAM (DMG DDE DRAM) and triple material gate dual drain electrode DRAM (TMG DDE DRAM) is done in terms of retention time and sense margin. The performance parameters with different device dimensions and bias conditions are analyzed. It is observed that the proposed DRAMs work well even when the dimensions are scaled down. In addition, the proposed DRAMs have comparable performance with the conventional DRAMs and provide better performance when compared with other dopingless DRAM. Retention times of 430 ms and 370 ms, sense margins of 130 nA and 101 nA are achieved with TMG DDE DRAM and DMG DDE DRAM respectively.

A Technology Path for Scaling Embedded FeRAM to 28 nm and Beyond With 2T1C Structure

Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130 nm node with 1T1C structure. To scale FeRAM to 28 nm or beyond, a high aspect ratio embedded dynamic random-access memory (eDRAM)-like 3-D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantage of a back-end-of-line (BEOL) oxide channel writing transistor, a small planar ferroelectric (FE) capacitor, and a silicon logic reading transistor. First, the proof-of-concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability toward 28 nm or beyond was simulated with array-level parasitics. Thanks to the transconductance reading out mechanism, a 900 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FE capacitor in 2T1C could significantly reduce energy consumption 6.4– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6\times $ </tex-math></inline-formula> compared to the traditional 1T1C FeRAM with similar cell area at 28 nm. Moreover, the area ratio between the FE capacitor and the read transistor is investigated both experimentally and with SPICE simulation, where adjustment of the pulsing scheme is needed for the maximum sense margin to occur. Finally, the performance at 7 nm is estimated in terms of read/write energy and cell area.

Design Space Exploration of Ferroelectric Tunnel Junction Toward Crossbar Memories

We perform a simulation-based analysis on the potential of emerging ferroelectric tunnel junctions (FTJs) as a memory device for crossbar arrays. Though FTJs are promising due to their low power switching characteristics compared to other emerging technologies, the greatest challenge for FTJs is the tradeoff between integration density and read performance. Our analysis highlights the need to co-optimize the ferroelectric thickness of the FTJ and read/write voltages to achieve proper functionality at large array sizes. Our analysis shows that FTJ-based crossbar achieves 93% higher sense margin at isoread power of 116 nW (per bit), but this FTJ design comes at a cost of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.28\times $ </tex-math></inline-formula> higher write power at isowrite time of 250 ns. In response, we study the potential tradeoffs of design points outside the feasible region to understand what device characteristics are desired to overcome such challenges.