Sense Amplifier Design Research Articles

Design and Analysis of Low Power Latch Sense Amplifier

Technology scaling has enabled us to integrate both memory and logic circuits on a single chip. However, the performance of embedded memory and its peripheral circuits can adversely affect the speed and power of the overall system. Sense amplifier is one of the important peripheral circuits in the memory as it strongly influences the memory access times. It retrieves the stored data from the memory array by amplifying the small differential signal on the bit lines. Therefore, the power dissipated within the on-chip caches, both active and standby will become dominant parts of the total power consumption of the chip. In view of the above, there apparent urgency to address the power dissipation of chip. The main objective of this paper is the design of Low Power Sense Amplifier. For lowering the power dissipation three techniques are used voltage scaling, half Vdd precharge circuits and VTCMOS. The most efficient way of reducing power dissipation is by scaling down the power supply voltage.

Design and Analysis of Low Power Latch Sense Amplifier

Design and Analysis of Low Power Latch Sense Amplifier

Design and Implementation of a Low Supply Voltage Voltage Type Sense Amplifier with Low Current Consumption for RFID Transponder

Current or voltage-type sense amplifier (SA) is the key element for sensing process of RFID transponder EEP-ROM. The performance of the EEPROM is influenced by the SA features like memory access time, power dissipation and the reliability. However, larger current or power dissipation put limitations on using current type SA with respect to voltage type SA. A low voltage SA with lower current consumption is presented in this research work, which is compatible with the low power applications like RFID transponder EEPROM. In this research, 0.18μm process is employed to design the low voltage SA with lower power consumption. The simulated results of the output showed that voltage type SA is able to operate under a low power supply voltage (VDD). In addition, only 32 μA current is dissipated by the modified voltage type SA during read period. Moreover, the proposed voltage type SA provides better reliability than the circuits presented in other research papers.

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

In this paper, we propose a new independent-gate, process-variation-tolerant double-gate (DG) FinFET based sense amplifier design. The new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate FinFET (DG FinFET) device for dynamic compensation against process variation. The proposed design improves the sensing delay and show excellent tolerance to process variations as compared to independent-gate sense amplifier (IGSA). The primary advantage of the proposed amplifier over previously reported sense amplifier is the low-noise voltage and large critical charge, making it more stable against single event upsets. Failure probability of the proposed design against process parameter variations is analyzed through Monte Carlo analysis.

New design of sense amplifier for EEPROM memory

We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method, having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V, simulation results showed that the charge time is 35 ns in the proposed sense amplifier, and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications, and has a silicon area of only 240 μm2.

New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications

This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-μm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz--1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Double-gate (DG) transistor has emerged as one of the most promising devices for nano-scale circuit design. In this paper, we propose a high-performance and robust sense-amplifier design using independent gate control in symmetric and asymmetric DG devices for sub-50-nm technologies. The proposed sense amplifier has better performance (30%-35% less sensing delay) and robustness (60%-80% less minimum input bit-differential for correct operation considering 10% worst case silicon thickness mismatch) compared to the connected gate design. Hence, the proposed design successfully demonstrates the benefit of using independent gate control in DG devices for efficient circuit design in sub-50-nm regime.

Yield and matching implications for static RAM memory array sense-amplifier design

The effects of MOS transistor mismatch upon sense-amplifier yield in synchronous static RAM memories is investigated. The matching characteristics of the two transistor layout styles are compared, a general formula is derived for calculating the statistical likelihood of the sense amplifier failing to read correct data given transistor size and input differential voltage, recommendations are made for optimizing size/speed/reliability trade-offs.

A low voltage SRAM for embedded applications

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 /spl mu/W. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 /spl mu/W. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.

Single event mirroring and DRAM sense amplifier designs for improved single-event-upset performance

This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9 k/spl Omega/ L-resistor hardening scheme provides greater than 24-fold improvement in critical charge over a significant part of the sensing period. Also proposed is a novel single event (SE) mirroring concept for SEU hardening of DRAMs. This concept has been implemented for hardening the bitlines to hits on diffusion regions connected to the lines during the highly susceptible high-impedance state of the bitlines. It is shown to result in over 26-fold improvement in the level of critical charge using a 2pF dynamic capacitive coupling. >

Design and analysis of a high-speed sense amplifier for single-transistor nonvolatile memory cells

Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds equal to or better than those achievable by memory arrays using two transistors per cell. Other circuit techniques were used to improve the circuit-noise immunity as well as sensitivity to critical mask misalignments including the use of output latches, dummy bit lines and decoded odd/even reference-memory-cell selection. The circuit was implemented on a 32 k EPROM memory chip using 1.5 m N-well CMOS process

An improved latching pulse design for dynamic sense amplifiers

A generalized optimal latching pulse for dynamic sense-amplifier design has been derived. The model equations account for threshold-voltage imbalance bit-line capacitance imbalance, current-gain imbalance, gate capacitance and intra-bit-line capacitive coupling effect, channel-length modulation, source-body effect, and temperature sensitivity in a unified manner. Computer simulations of the analytical equations, including those effects, are presented. The analytical results provide physical insight into sensing speed and the sensitivity of optimized waveforms in terms of process imbalances, device model parameters, and circuit design variables. A design implementation for fast sense-amplifier operation is also presented to demonstrate the utility of the model equations for practical application.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sense amplifier design is key to 1-transistor cell in 4096-bit RAM : C. Kuo. N. Kitagawa, E. Ward and P. Drayer. Electronics (Sept. 1973). p. 116

Sense amplifier design is key to 1-transistor cell in 4096-bit RAM : C. Kuo. N. Kitagawa, E. Ward and P. Drayer. Electronics (Sept. 1973). p. 116

A High-Speed Direct-Coupled Magnetic Memory Sense Amplifier Employing Tunnel-Diode Discriminators

Because of a multiplicity of conflicting requirements, sense amplifier design is probably the most difficult circuit problem in a large, high-speed digital computer memory. The requirements include absence of pattern sensitivity, controllable input impedance, a wide band pass, stable gain, high common mode rejection, the ability to handle bipolar signals, stable reference levels, a fast comparator, low threshold level, and, one hopes, low cost. This paper discusses a new circuit which fulfills these requirements with simplicity. Intended for large size (> 1000 words) random access core and thin-film memories, it is capable of handling, for example, a 50-mv ``1'' with approximately 50-nsec delay for transmission and comparison. Common mode signals of as high as 10 volts do not affect discriminator performance. Two key features of the circuit are the use of a dc-coupled, ``long-tail pair'' preamplifier and a pair of tunnel diodes as the discrimination elements. The dc-coupled differential preamplifier provides high common mode rejection, stable gain, is pattern insensitive, and has the ability to handle bipolar signals. The tunnel diode provides a superior discriminator, since it is fast, and has a low-level threshold which is controllable and stable with temperature variations. Thus, requirements on the magnitude and stability of the preamplifier gain are less severe. Design equations are derived and a complete dc worst-case analysis is performed. Variations in the circuit for several specific applications and experimentally determined performance data are described. The generalized problem of a tunnel-diode discriminator used with a preamplifier is treated in Appendix II.

Design of Memory Sense Amplifiers

A fundamental problem in the design of fast (4 to 6 ?sec) word oriented memories using S-1 core material is the realization of a sensing amplifier which has the multitude of required properties. The sense amplifier is usually required to provide stable gain for bipolarity signals, to introduce a negligible delay into the signal path, to avoid dc level shift, to recover within a short time following the enable (or inhibit) noise, to provide a stable discrimination level, etc. Although many sense amplifier designs have appeared in the literature, none, to the authors' knowledge, are eminently suitable for a 4- to 6-?sec memory under the condition of ``worst case input pattern''?a long sequence of unipolarity pulses interspaced with ``blasts'' of enable noise. The basic requirements for a sense amplifier suitable for a word oriented memory in conjunction with a required memory cycle are discussed. This newly developed sense amplifier and its operation and design are presented. Emphasis is placed on the evolution of the techniques and circuits presented, and several other approaches pursued during the design are also described. The authors also comment on possible future approaches to the sensing problem.