A low voltage SRAM for embedded applications

Abstract

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 /spl mu/W. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 /spl mu/W. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.