Abstract

A 4 Kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 volts with a RMS run power (1 MHz) of 22 /spl mu/W. The circuit operates at maximum frequency of 38 MHz at a supply voltage of 1.6 volts with a RMS run power (1 MHz) of 32 /spl mu/W. The design utilizes a sub-blocked array architecture as well as selective use of NOR/NAND based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.

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