Design and Analysis of Low Power Latch Sense Amplifier

Abstract

Technology scaling has enabled us to integrate both memory and logic circuits on a single chip. However, the performance of embedded memory and its peripheral circuits can adversely affect the speed and power of the overall system. Sense amplifier is one of the important peripheral circuits in the memory as it strongly influences the memory access times. It retrieves the stored data from the memory array by amplifying the small differential signal on the bit lines. Therefore, the power dissipated within the on-chip caches, both active and standby will become dominant parts of the total power consumption of the chip. In view of the above, there apparent urgency to address the power dissipation of chip. The main objective of this paper is the design of Low Power Sense Amplifier. For lowering the power dissipation three techniques are used voltage scaling, half Vdd precharge circuits and VTCMOS. The most efficient way of reducing power dissipation is by scaling down the power supply voltage.