Abstract

Sense amplifiers play an important role in memories like Dynamic Random Access (DRAM) and Static Random Access (SRAM) for read operations. Sense amplifier is one of the peripheral circuits in memories that are placed in each column of the memory array. A sense amplifier compares the bit line voltage and its complement, and then amplifies it to rail to rail output voltages. In this project, several latch type sense amplifier have been designed and simulated using 90nm CMOS technology with a supply voltage of 1.2V. Sensing delay is one of the important factors in sense amplifier design and it will be calculated for all sense amplifiers by performing voltage scaling.

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