IMPLEMENTATION OF LATCH TYPE SENSE AMPLIFIER

Abstract

Sense amplifiers plays an important role in memories like Dynamic Random Access (DRAM) and Static Random Access (SRAM) for read and write operations. A sense amplifier compares the bit line voltage and its complement amplifies it to rail to rail output voltages. In this project, we mainly concentrated on the write operation. Sense amplifier is one of the peripheral circuits in memories that are placed in each column of the memory array. In this project, we discuss some of the sense amplifiers circuits and they are simulated in SPICE. An analytical model has been derived and simulated using 90nm CMOS technology with a supply voltage of 1.2v. When the input voltage difference of a sense amplifier is greater than the offset voltage (VOS), the sense amplifier correctly detect the signal and amplifier it to correct logic levels. In an ideal case, the offset voltage of a sense amplifier is zero. Therefore, the sense amplifier can correctly sense the voltage present in the input bitlines, unless the differential bitline voltage is zero. Practically, the offset voltage is not zero because of the mismatch between the transistors. Hence, the differential bitline voltage must be greater than the offset voltage of the sense amplifier for correct sensing operation. Sensing delay, latching delay is one of the important factors in sense amplifier design. So the sense delay and latching delay of sense amplifier has been calculated for various supply voltages. Finally, the current mode sense amplifier has low sensing delay and latching delay compared to other latch type sense amplifiers.