Semiconductor Wafer Processing Research Articles

Crack Formation Reduction on Diamond-Paste Abrasive Processing of Silicon-Carbide Semiconductor Wafers

Crack Formation Reduction on Diamond-Paste Abrasive Processing of Silicon-Carbide Semiconductor Wafers

A Study on the Control Method of 6-DOF Magnetic Levitation System Using Non-Contact Position Sensors

Recently, due to the development of semiconductor technology, high-performance memory and digital convergence technology that integrates and implements various functions into one semiconductor chip has been regarded as the next-generation core technology. In the semiconductor manufacturing process, various motors are being applied for automated processes and high product reliability. However, dust and shaft loss due to mechanical friction of a general motor system composed of motor-bearing are problematic for semiconductor wafer processing. In addition, in the edge bread remove (EBR) process after the photoresist application process, a nozzle position control system for removing unnecessary portions of the wafer edge is absolutely necessary. Therefore, in this paper, in order to solve the problems occurring in the semiconductor process, a six-degrees-of-freedom (6-DOF) magnetic levitation system without shaft and bearing was designed for application to the semiconductor process system; and an integrated driving control algorithm for 6-DOF control (levitation, rotation, tilt (Roll-Pitch), X-Y axis movement) using the force of each current component derived through current vector control was proposed. Finally, the 6-DOF magnetic levitation system with the non-contact position sensors was fabricated and the validity of the 6-DOF magnetic levitation control method proposed in this paper was verified through a performance test using a prototype.

Highly effective transfer of micro-LED pixels to the intermediate and rigid substrate with weak and tunable adhesion by thiol modification.

Based on transfer printing technology, micro-LED pixels can be transferred to different types and sizes of driving substrates to realize displays with different application scenarios. To achieve a successful transfer, GaN-based micro-LEDs first need to be separated from the original epitaxial substrate. Here, micro-LED pixels (each size 25 μm × 30 μm) on the sapphire substrate were transferred to a flexible semiconductor wafer processing (SWP) tape that is strongly sticky by conventional laser lift-off (LLO) techniques. The pixels on the SWP tape were then transferred by using a sacrificial layer of non-crosslinked oligomeric polystyrene (PS) film onto the intermediate and rigid substrate (IRS) with weak and tunable adhesion by thiol (-SH) modification. The electrode of the micro-LED is Au metal, which forms Au-S bonds with the surface of the IRS to fix the pixels. The rigid substrate helps ensure that the pixel spacing is almost unchanged during the stamp transfer process, and the weak and tunable adhesion facilitates the pixels being picked up by the stamp. The experimental results demonstrate that the pixels can be efficiently transferred to the IRS by LLO and sacrificial layer-assistance, which will provide the possibility of achieving the further transfer of pixels to different types and sizes of driving substrates by a suitable transfer stamp. The transfer process details are discussed, which can provide insights into the transfer of micro-nano devices through polymer sacrificial layers.

Observer design for a nonlinear heat equation: Application to semiconductor wafer processing

In this paper, the problem of observer design for a class of 1D nonlinear heat equations with pointwise in-domain temperature measurements is addressed. A pointwise measurement injection observer is designed and the robust convergence of its estimation error in presence of bounded distributed perturbations is established by verifying input-to-state stability. The obtained convergence conditions express the underlying interplay between heat conduction and radiation and include specific dependencies on the sensor locations which are the main degrees of freedom in the design approach. The theoretical results are experimentally validated on a semiconductor wafer processing unit.

Non-contact grinding/thinning of silicon carbide wafer by pure EDM using a rotary cup wheel electrode

The significantly increased stability of third-generation semiconductors, both mechanically and chemically, presents a significant challenge to traditional wafer grinding. This study develops pure electrical discharge machining as an alternative for non-contact wafer grinding and thinning to achieve high precision and low cost. This method employs a copper-made rotary cup wheel as the tool electrode to replace the conventional diamond wheel to realize electrical discharge grinding. A prototype is built to evaluate the new process with single-crystal SiC. Aiming at ultra-precision machining, the material response of SiC to both single and consecutive discharge is elucidated. The influencing mechanism of pulse conditions on hard, brittle crystalline SiC material is demonstrated via experiments and simulation. Further, the material removal behavior, grinding stability, surface integrity, wafer shape accuracy, and process-induced subsurface damage are comprehensively investigated via single and consecutive discharge experiments under various conditions. In addition, the extreme precision that is achievable by contemporary EDM technology is explored. As a result, a 30 μm thin Φ20 mm SiC wafer with a subsurface damaged layer <1 μm was obtained, showing the potential of EDM for the processing of third-generation semiconductor wafers.

Movement Control Method of Magnetic Levitation System Using Eccentricity of Non-Contact Position Sensor

This paper presents a method of utilizing a non-contact position sensor for the tilting and movement control of a rotor in a rotary magnetic levitation motor system. This system has been studied with the aim of having a relatively simple and highly clean alternative application compared to the spin coater used in the photoresist coating process in the semiconductor wafer process. To eliminate system wear and dust problems, a shaft-and-bearing-free magnetic levitation motor system was designed and a minimal non-contact position sensor was placed. An algorithm capable of preventing derailment and precise movement control by applying only control without additional mechanical devices to this magnetic levitation system was proposed. The proposed algorithm was verified through simulations and experiments, and the validity of the algorithm was verified by deriving a precision control result suitable for the movement control command in units of 0.1 mm at 50 rpm rotation drive.

Characterization of film materials in wafer processing technology development by XPS

A brief introduction reviews the changes that have occurred in semiconductor wafer processing, which, coupled with developments in X ray Photoelectron Spectroscopy, XPS, instrumentation, have led to XPS becoming a primary materials analysis tool in this industry. Three specific examples illustrating the use of XPS and Angle resolved XPS, ARXPS, are then presented. These are nitridation processing of high k gate material (HfO2 based); the monitoring of Al content and chemistry in a 10A TiAlN film (a metal gate add on process to high k); and deposition of diamond-like amorphous C films (a candidate for hard mask applications in DRAM, NAND flash, and NOR flash memories).

반도체 웨이퍼 열공정에 사용되는 파워단자부의 전기-열 해석

반도체 웨이퍼 열공정에 사용되는 파워단자부의 전기-열 해석

多品種小量生産履歴データに基づく半導体ウェハ加工プロセス予測制御モデルの構築手法 : MCMC法による統計的予測モデル構築のエンジニアリングサービス実現(事例研究, サービス工学)

多品種小量生産履歴データに基づく半導体ウェハ加工プロセス予測制御モデルの構築手法 : MCMC法による統計的予測モデル構築のエンジニアリングサービス実現(事例研究, サービス工学)

Optimizing the dicing saw parameters of 60 μm wafer dicing street

Wafer surface dicing chipping can expand to impact chip circuits, which may cause serious defects during the IC assembly process, potentially resulting in IC circuit function failure. Throughout the semiconductor wafer process, the street design of wafer dicing is gradually narrowed, that raising the importance of controlling chipping performance. To obtain the key factor of dicing parameters, this paper studies and evaluates the dicing of a wafer with a street width of 60 µm and thickness of 200 µm using mechanical dicing saw and diamond dicing blade. In this design of experiment, experimental data were analyzed using analysis of variance to obtain key parameters for surface chipping. The results show that high cutting spindle speed of 50,000 rpm with shallow cutting depth of 50 µm provides better surface chipping performance, and improves chipping of abnormal base with a blade dicing saw.

Pro-Inflammatory and Pro-Fibrogenic Effects of Ionic and Particulate Arsenide and Indium-Containing Semiconductor Materials in the Murine Lung.

We have recently shown that the toxicological potential of GaAs and InAs particulates in cells is size- and dissolution-dependent, tending to be more pronounced for nano- vs micron-sized particles. Whether the size-dependent dissolution and shedding of ionic III-V materials also apply to pulmonary exposure is unclear. While it has been demonstrated that micron-sized III-V particles, such as GaAs and InAs, are capable of inducing hazardous pulmonary effects in an occupational setting as well as in animal studies, the effect of submicron particles (e.g., the removal of asperities during processing of semiconductor wafers) is unclear. We used cytokine profiling to compare the pro-inflammatory effects of micron- and nanoscale GaAs and InAs particulates in cells as well as the murine lung 40 h and 21 days after oropharyngeal aspiration. Use of cytokine array technology in macrophage and epithelial cell cultures demonstrated a proportionally higher increase in the levels of matrix metalloproteinase inducer (EMMPRIN), macrophage migration inhibitory factor (MIF), and interleukin 1β (IL-1β) by nanosized (n) GaAs and n-InAs as well as As(III). n-GaAs and n-InAs also triggered higher neutrophil counts in the bronchoalveolar lavage fluid (BALF) of mice than micronscale particles 40 h post-aspiration, along with increased production of EMMPRIN and MIF. In contrast, in animals sacrificed 21 days after exposure, only n-InAs induced fibrotic lung changes as determined by increased lung collagen as well as increased levels of TGF-β1 and PDGF-AA in the BALF. A similar trend was seen for EMMPRIN and matrix metallopeptidase (MMP-9) levels in the BALF. Nano- and micron-GaAs had negligible subacute effects. Importantly, the difference between the 40 h and 21 days data appears to be biopersistence of n-InAs, as demonstrated by ICP-OES analysis of lung tissue. Interestingly, an ionic form of In, InCl3, also showed pro-fibrogenic effects due to the formation of insoluble In(OH)3 nanostructures. All considered, these data indicate that while nanoscale particles exhibit increased pro-inflammatory effects in the lung, most effects are transient, except for n-InAs and insoluble InCl3 species that are biopersistent and trigger pro-fibrotic effects. These results are of potential importance for the understanding the occupational health effects of III-V particulates.

Application of a Plasma Arc Lamp for Thermal Processing of Semiconductor Wafers

This paper describes the application of a vortex water wall high-pressure argon lamp for a semiconductor annealing process. These lamps have been designed to operate up to a 500-kW power level, have a continuous spectrum, similar to daylight, and have been used to characterize solar cells. Precise control of the radiated power generated by the lamps is required, which, in turn, requires an accurate electrothermooptical dynamic model of the lamp and an optothermal model of the wafer. This paper discusses general aspects regarding the modeling of the system consisted of the lamp and the wafer. The main contributions of the paper are the following: 1) a simplified means of relating the radiation exiting the lamp to the electrical power injected into the lamp, taking into account radiation from an isothermal core and absorption in the cold swirling argon gas, the water wall, and the quartz envelope; and 2) a model to describe energy exchange between the lamp and the wafer and experimental results to indicate the good agreement between the model and the actual apparatus. Two companion papers discuss the details of the arc model and the discrete-time control algorithms developed to model the wafer subsystem and the arc subsystem.

Physics-Based Circuit Model for a Water-Wall High-Temperature Arc Lamp Using Finite Volume Method

High-Temperature arc lamps are used for thermal processing of semiconductor wafers. A vortex water wall on the inner surface of the lamp's enclosure is used to provide cooling for the glass. It has been experimentally observed that above certain levels of injected energy the arc shows an unstable behaviour and is self-extinguished. In this paper, a physics-based model for the water-wall high-temperature arc lamp is derived and implemented in the form of an equivalent electrical circuit. The equivalent circuit is then coupled to the flash power supply equivalent circuit to validate the derived model against experimental voltage and current waveforms.

Fabrication of a Monolithic Array of Three Dimensional Si-based Ion Traps

Segmented linear ion trap arrays are versatile devices that are increasingly used to study quantum physics and demonstrate the fundamental principles of quantum information processing. Traps with three-dimensional (3-D) electrode geometries can create a superior confining potential for ions. However, the realization of a monolithic 3-D microchip trap with scalable fabrication technology remains challenging. In this paper the microfabrication of a monolithic array of 3-D ion microtraps in a semiconductor chip is presented. The electrode structure is formed by micromachining a silica-on-silicon wafer and metallizing the dielectric with gold. The fabrication method uses conventional semiconductor wafer processing tools and techniques. The specific operating characteristics which demonstrate the suitability of the chosen material system and fabrication process are presented.

Fuzzy-based risk priority number in FMEA for semiconductor wafer processes

Semiconductor wafer manufacturing processes are considered to be complex and require considerable manpower and financial investment. Effective control to promote wafer yield is thus a very important issue. Many computational problems in traditional failure mode approaches, such as variable selection and data collection, are far too dependent on the experience of engineers, with a lack of specifically quantified values. Therefore, there are significant differences between the results of research and the actual processes. Although several researchers have revised the failure mode computation, the occurrence results continue to differ from the actual quantified values. The potential failure mode in semiconductor wafer manufacturing processes is effectively discussed using linguistic fuzzy variables to replace the severity and detection in the failure mode for re-calculation and sorting, along with the occurrence acquired from the wafer processes yield change. Based on the results of engineering experiments, the use of a risk priority number can effectively overcome the problem of a lack of objectivity in the traditional failure mode and effect analysis, as well as accurately distinguish the priority of the key failure factors so that the research results become more complete.

The Process of Plasma Chemical Photoresist Film Ashing from the Surface of Silicon Wafers

At present, the research for finding new technical methods of treating materials with plasma, including the development of energy and resource saving technologies for microelectronic manufacturing, is particularly actual.In order to improve the efficiency of microwave plasma chemical ashing of photoresist films from the surface of silicon wafers a two-stage process of treating was developed. The idea of the developed process is that wafers coated with photoresist are pre-heated by microwave energy. This occurs because the microwave energy initially is not spent on the excitation and maintenance of a microwave discharge but it is absorbed by silicon wafers which have a high tangent of dielectric losses. During the next step after the excitation of the microwave discharge the interaction of oxygen plasma with a pre-heated photoresist films proceeds more intensively. The delay of the start of plasma forming process in the vacuum chamber of a plasmatron with respect to the beginning of microwave energy generation by a magnetron leads to the increase of the total rate of photoresist ashing from the surface of silicon wafers approximately 1.7 times. The advantage of this method of microwave plasma chemical processing of semi-conductor wafers is the possibility of intensifying the process without changing the design of microwave discharge module and without increasing the input microwave power supplied into the discharge.

Fabrication of Responsive, Softening Neural Interfaces

AbstractA novel processing method is described using photolithography to pattern thin‐film flexible electronics on shape memory polymer substrates with mechanical properties tailored to improve biocompatability and enhance adhesion between the polymer substrate and metal layers. Standard semiconductor wafer processing techniques are adapted to enable robust device design onto a variety of softening substrates with tunable moduli. The resulting devices are stiff enough (shear modulus of ≈700 MPa) to assist with device implantation and then soften in vivo (≈300 kPa) approaching the modulus of brain tissue (≈10 kPa) within 24 h. Acute in vivo studies demonstrate that these materials are capable of recording neural activity. Softening multi‐electrode arrays offer a highly customizable interface, which can be optimized to improve biocompatibility, enabling the development of robust, reliable neural electrodes for neural engineering and neuroscience.

Self-consistent simulation study on magnetized inductively coupled plasma for 450 mm semiconductor wafer processing

The characteristics of weakly magnetized inductively coupled plasma (MICP) are investigated using a self-consistent simulation based on the drift–diffusion approximation with anisotropic transport coefficients. MICP is a plasma source utilizing the cavity mode of the low-frequency branch of the right-hand circularly polarized wave. The model system is 700mm in diameter and has a 250mm gap between the radio-frequency window and wafer holder. The model chamber size is chosen to verify the applicability of this type of plasma source to the 450mm wafer process. The effects of electron density distribution and external axial magnetic field on the propagation properties of the plasma wave, including the wavelength modulation and refraction toward the high-density region, are demonstrated. The restricted electron transport and thermal conductivity in the radial direction due to the magnetic field result in small temperature gradient along the field lines and off-axis peak density profile. The calculated impedance seen from the antenna terminal shows that MICP has a resistance component that is two to threefold higher than that of ICP. This property is practically important for large-size, low-pressure plasma sources because high resistance corresponds to high power-transfer efficiency and stable impedance matching characteristics. For the 0.665Pa argon plasma, MICP shows a radial density uniformity of 6% within 450mm diameter, which is much better than that of nonmagnetized ICP.

A Wafer-level System Integration Technology Incorporates Heterogeneous Devices

A pseudo-SoC technology incorporating heterogeneous devices has been developed by applying a wafer-level system integration technology. The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and redistribution layer, respectively. The individual heterogeneous devices are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper describes the heterogeneous devices integration technologies and focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications.

IDDQ Test Practice in Nanotechnologies

As semiconductor wafer process technology went into nanotech level, IDDQ test faced tremendous challenges than it ever did due to high intrinsic leakage. A case study of IDDQ test in Availink ASICs in 130nm and 65nm process technologies demonstrates that IDDQ test is still feasible. The scheme includes IDDQ test vectors precise selection/generation, IDDQ measurement with high resolution/repeatability, proper statistical post processing algorithm in outlier detection, results verification, etc. As a result, IDDQ test is still considerable in manufacturing test strategy in nanotechnologies era.