Semiconductor Wafer Fabrication Facilities Research Articles

Data-Driven Production Planning Models for Wafer Fabs: An Exploratory Study

Cycle time, which is of order of ten weeks for most products in semiconductor wafer fabrication facilities (wafer fabs), must be explicitly considered in production planning models. Cycle times depend nonlinearly on the resource workload in a wafer fab. Different data-driven (DD) production planning formulations are studied in this paper. Such formulations are based on a set of system states representing the congestion behavior of a wafer fab with work in process (WIP) and resulting output levels. Different WIP-output relations in the DD formulations are investigated. In addition, different methods are proposed to gather representative sets of system states. The DD formulations are compared with the Allocated Clearing Function (ACF) formulation with respect to profit and cost values using simulation models of a scaled-down and a large-sized multiproduct wafer fab, respectively. The simulation results show that some DD variants are able to outperform the ACF formulation under several experimental conditions.

Data-driven aggregate modeling of a semiconductor wafer fab to predict WIP levels and cycle time distributions

In complex manufacturing systems, such as a semiconductor wafer fabrication facility (wafer fab), it is important to accurately predict cycle times and work-in-progress (WIP) levels. These key performance indicators are commonly predicted using detailed simulation models; however, the detailed simulation models are computationally expensive and have high development and maintenance costs. In this paper, we propose an aggregate modeling approach, where each work area, i.e., a group of functionally similar workstations, in the wafer fab is aggregated into a single-server queueing system. The parameters of the queueing system can be derived directly from arrival and departure data of that work area. To obtain fab-level predictions, our proposed methodology builds a network of aggregate models, where the network represents the entire fab consisting of different work areas. The viability of this method in practice is demonstrated by applying it to a real-world wafer fab. Experiments show that the proposed model can make accurate predictions, but also provide insights into the limitations of aggregate modeling.

Hierarchical Decision-Making for Qualification Management in Wafer Fabs: A Simulation Study

A qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is discussed. The stepper equipment needs to be qualified to process lots that belong to different families. Stepper- and family dependent qualification time windows exist. Time windows can be reinitialized if required and can be extended by on-time processing of lots from qualified families. A hierarchical approach is proposed. The base-level provides a dispatching strategy that takes into account qualification decisions, while the mid-level consists of a mixed integer linear program (MILP) for making qualification decisions. The top-level comprises a linear program (LP) that computes target quantities for the families on the steppers in each period of the planning window taking into account fab-wide objectives. In addition to an LP formulation with conventional capacity constraints, we provide a formulation where clearing functions are used to represent the congestion of the wafer fab. We also discuss how to anticipate the behavior of the mid-level on the top-level. Results of simulation experiments where the hierarchical approach is applied in a rolling horizon manner demonstrate that the LP-based approaches outperform a heuristic to determine the target quantities. Among the LP formulations, the ones with clearing functions perform best. We also demonstrate the value of anticipation. Note to Practitioners—A hierarchical approach is designed to decide when tools in wafer fabs have to be qualified for a certain lot family. Qualification-related decisions are highly relevant because qualifications are costly and take a lot of time. The top-level determines target quantities for each family based on linear programming. The mid-level is formed by a MILP. A dispatching scheme to implement the qualification decisions provides the base-level. The hierarchical approach is assessed in a rolling horizon setting using a simulation model of a 200mm wafer fab. The benefit of the different levels of the hierarchy is demonstrated by simulation experiments.

Practical Q-Learning-Based Route-Guidance and Vehicle Assignment for OHT Systems in Semiconductor Fabs

We introduce and analyze vehicle-allocation algorithms for overhead hoist transport (OHT) systems in semiconductor wafer-fabrication facilities (fabs). OHT is the most widely used type of automated material-handling system in fabs, comprising hundreds of vehicles delivering lots between processing machines. Timely transport unit delivery by OHT systems are critical to the efficient overall operation of a modern fab. We first describe the limitations of current OHT vehicle-allocation algorithms, and then detail an improved system that can be implemented in practical environments to manage the operation of hundreds of OHT vehicles. Our proposed system is based on reinforcement learning. In particular, it uses Q-learning-based dynamic vehicle-allocation algorithms to examine traffic conditions and then allocate an OHT vehicle to a delivery job. We propose multiple algorithms based on the Q-learning approach and compare their performance with that of conventional allocation approaches, which reveals the appropriate algorithms for use in industry. We demonstrate that our algorithms are efficient and sufficiently fast to be used in a practical large-scale setting.

A matheuristic for making order acceptance decisions in multi-product, multi-stage manufacturing systems

We discuss a planning model with load-dependent lead times for making order acceptance decisions in multi-product, multi-stage manufacturing systems. Semiconductor wafer fabrication facilities (wafer fabs) belong to this class of manufacturing systems. A profit-based objective function is considered. Clearing functions are used in the planning formulation to correctly represent the lead time behavior in the case of a congested system. Order acceptance decisions are made with respect to flexible due dates, i.e., it is possible to reject certain orders if there is not enough capacity. Such acceptance decisions are important, for instance, in short-term demand supply matching algorithms that are crucial for demand fulfillment and available to promise decisions in semiconductor manufacturing. The resulting planning problem is formulated as a mixed integer linear program. We first show that the resulting planning problem is NP-hard. Hence, computationally tractable approaches must be designed. Therefore, variable neighborhood search is hybridized with linear programming to solve large-sized problem instances in reasonable amount of computing time in the present paper. Results of computational experiments for problem instances that are derived from a scaled-down wafer fab simulation model are provided and analyzed. The computational results demonstrate that the proposed matheuristic outperforms time-based decomposition approaches from the literature.

Matheuristics for Qualification Management Decisions in Wafer Fabs

In this paper, a qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is studied. The stepper machines, a common bottleneck in many wafer fabs, must be qualified to process lots of different families. A qualification time window is associated with each stepper and family. It can be reinitialized as needed and can be extended by on-time processing of lots from qualified families. Fast heuristic approaches, among them a Greedy Randomized Adaptive Search Procedure (GRASP), are proposed to solve large-sized problem instances using a small amount of computing time. The qualification decisions modeled by binary decision variables are made by heuristic procedures that exploit the problem structure while the real-valued quantities for each family and stepper are computed using linear programming. Computational experiments based on randomly generated problem instances are conducted. The results show that the proposed matheuristics are able to quickly provide high-quality solutions.

Bi-criteria parallel batch machine scheduling to minimize total weighted tardiness and electricity cost

A bi-criteria scheduling problem for parallel identical batch processing machines in semiconductor wafer fabrication facilities is studied. Only jobs belonging to the same family can be batched together. The performance measures are the total weighted tardiness and the electricity cost where a time-of-use (TOU) tariff is assumed. Unequal ready times of the jobs and non-identical job sizes are considered. A mixed integer linear program (MILP) is formulated. We analyze the special case where all jobs have the same size, all due dates are zero, and the jobs are available at time zero. Properties of Pareto-optimal schedules for this special case are stated. They lead to a more tractable MILP. We design three heuristics based on grouping genetic algorithms that are embedded into a non-dominated sorting genetic algorithm II framework. Three solution representations are studied that allow for choosing start times of the batches to take into account the energy consumption. We discuss a heuristic that improves a given near-to-optimal Pareto front. Computational experiments are conducted based on randomly generated problem instances. The varepsilon -constraint method is used for both MILP formulations to determine the true Pareto front. For large-sized problem instances, we apply the genetic algorithms (GAs). Some of the GAs provide high-quality solutions.

Qualification Management in Wafer Fabs: Optimization Approach and Simulation-Based Performance Assessment

Machines need to be individually qualified to run lots of certain families in semiconductor wafer fabrication facilities (wafer fabs). A qualification time window that lasts a couple of days is associated with each family and each tool. The time window can be reinitialized with additional qualification effort as needed and can be extended by on-time processing of qualified families. A mixed-integer linear programming formulation is proposed. The objective function takes into account the backlog costs and inventory holding costs. Moreover, it penalizes qualifications. The optimization approach is applied in a rolling horizon setting using a wafer fab simulation model. The demand for a planning window of several periods is derived using feedback from the shop floor. The results of the simulation experiments demonstrate that an appropriate tradeoff between production objectives and performed qualifications can be achieved by an appropriate configuration of the model. Note to Practitioners —In this article, we propose a mathematical programming-based approach to decide when the tools in wafer fabs have to be qualified for a certain family. These decisions have high practical relevance because qualifications are expensive and time-consuming. A dispatching scheme to implement the qualification decisions is designed. The overall approach is assessed in a rolling horizon setting using a simulation model of a large-scale wafer fab. An appropriate tradeoff between production and qualification goals can be achieved using the proposed approach.

Hybrid algorithms for the earliness–tardiness single-machine multiple orders per job scheduling problem with a common due date

In this paper, we study an earliness–tardiness scheduling problem for a single machine that is motivated by process conditions found in semiconductor wafer fabrication facilities (wafer fabs). In modern 300-mm wafer fabs, front opening unified pods (FOUPs) transfer wafers. The number of FOUPs is limited to avoid a congestion of the Automated Material Handling System. Several orders can be grouped in one FOUP. A nonrestrictive common due date for all the orders is assumed. Only orders that belong to the same family can be processed together in a single FOUP at the same time. We present a Mixed Integer Linear Programming (MILP) formulation for this problem. Moreover, we show that this scheduling problem is NP-hard. We propose several simple heuristics based on dispatching rules and assignment strategies from bin packing. Moreover, genetic algorithms are designed that assign the orders to the set of early and tardy orders, respectively. In addition, a random key genetic algorithm (RKGA) is described that proposes order sequences. The different algorithms are hybridized with job formation and sequencing heuristics. A more specialized algorithm that is based on the generalized assignment problem is presented for the special case of a single order family. Results of computational experiments based on randomly generated problem instances are presented. They demonstrate that the genetic algorithms perform well with respect to solution quality and computing time under a broad range of experimental conditions.

Rolling horizon, multi-product production planning with chance constraints and forecast evolution for wafer fabs

In this paper, we study production planning models for semiconductor wafer fabrication facilities (wafer fabs) that consider both safety stocks at the finished goods inventory level and workload-dependent lead times. The evolution of demand forecasts over time follows the multiplicative Martingale Model of Forecast Evolution (MMFE) for multiple products and is incorporated into the planning models via shortfall-based chance constraints, permitting the simultaneous determination of production quantities and safety stocks. We study two variants of this formulation, one that considers forecast updates and one that does not. A planning model with workload-dependent lead times that does not consider safety stocks is used for comparison. The performance of the planning models is assessed in a rolling horizon environment using a simulation model of a scaled-down wafer fab. We find that the chance-constrained model with forecast updates outperforms the one without forecast updates with respect to expected service level and profit. Both chance-constrained models outperform the model without safety stocks. These results indicate that considering forecast evolution in production planning models can lead to improved performance by exploiting the advance demand information provided by the forecast updates.

A Throughput Management System for Semiconductor Wafer Fabrication Facilities: Design, Systems and Implementation

Equipment throughput is one of the most critical parameters for production planning and scheduling, which is often derived by optimization techniques to achieve business goals. However, in semiconductor manufacturing, up-to-date and reliable equipment throughput is not easy to estimate and maintain because of the high complexity and extreme amount of data in the production systems. This article concerns the development and implementation of a throughput management system tailored for a semiconductor wafer fabrication plant (Fab). A brief overview of the semiconductor manufacturing and an introduction of the case Fab are presented first. Then, we focus on the system architecture and some concepts of crucial modules. This study also describes the project timescales and difficulties and discusses both tangible and intangible benefits from this project.

A Testbed for Simulating Semiconductor Supply Chains

In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed.

A hybrid scheduling approach for a two-stage flexible flow shop with batch processing machines

In this paper, we discuss a flexible flow shop scheduling problem with batch processing machines at each stage and with jobs that have unequal ready times. Scheduling problems of this type can be found in semiconductor wafer fabrication facilities (wafer fabs). We are interested in minimizing the total weighted tardiness of the jobs. We present a mixed integer programming formulation. The batch scheduling problem is NP-hard. Therefore, an iterative stage-based decomposition approach is proposed that is hybridized with neighborhood search techniques. The decomposition scheme provides internal due dates and ready times for the jobs on the first and second stage, respectively. Each of the resulting parallel machine batch scheduling problems is solved by variable neighborhood search in each iteration. Based on the schedules of the subproblems, the internal due dates and ready times are updated. We present the results of designed computational experiments that also consider the number of machines assigned to each stage as a design factor. It turns out that the proposed hybrid approach outperforms an iterative decomposition scheme where a fairly simple heuristic based on time window decomposition and the apparent tardiness cost dispatching rule is used to solve the subproblems. Recommendations for the design of the two stages with respect to the number of parallel machines on each stage are given.

Multi-Dimensional Dynamic Programming Algorithm for Input Lot Formation in a Semiconductor Wafer Fabrication Facility

Multi-Dimensional Dynamic Programming Algorithm for Input Lot Formation in a Semiconductor Wafer Fabrication Facility

Incorporating engineering process improvement activities into production planning formulations using a large-scale wafer fab model

In most semiconductor wafer fabrication facilities (wafer fabs), both production and engineering lots share the same expensive equipment. Production lots will be shipped to customers whereas engineering lots are used to support production and process development efforts. While production activities might lead to large revenue, engineering activities result in increased future output. In the present paper, we propose three different production planning formulations. The first formulation assumes a reduced available capacity for production due to engineering activities. Costs for production products are minimised. The second formulation is based on the idea that aggregated demand is available for engineering activities for the entire planning window. Costs for production and engineering products are minimised. Learning effects are incorporated to model the capacity increase due to engineering activities. The third model assumes that demand information for engineering activities is available only for the first period. In addition to learning effects, forgetting effects are modelled to provide an incentive to plan releases of engineering lots in later periods. Costs for production and engineering products and forgetting effects are minimised. The performance of the production planning models is assessed using a simulation model of a large-scale wafer fab including specific dispatching strategies to deal with production and engineering lots. The simulation results demonstrate that the second model slightly outperforms the third one when a rolling horizon approach is taken, while the second model provides significantly higher profit than the first one.

An efficient adaptive dispatching method for semiconductor wafer fabrication facility

To cope with uncertainty in semiconductor wafer fabrication facilities (fabs), scheduling methods are required to produce quick real-time responses. They should be well tuned to track the changes of a production environment to obtain good operational performance. This paper presents an efficient adaptive dispatching method (ADM) with parameters determined dynamically by real-time state information of fabs. ADM is composed of a dispatching rule considering both batch and non-batch processing machines to obtain improved fab-wide performance, several feature selection methods to determine key scheduling-related real-time state information, and a linear regression model to find the relations between the weighting parameters of the dispatching rule and the determined real-time state information. A real fab simulation model is used to demonstrate the proposed method. The simulation results show that ADM is adaptive to changing environment with better performance than a number of commonly used rules (such as FIFO, EDD, CR, LPT, LS, SRPT, and SPT) and an adaptive dispatching rule that considers only real-time ratio of hot jobs to the number of all jobs in a fab and the ratio of jobs with one third of photo steps left to the number of all jobs.

Grouping genetic algorithms for solving single machine multiple orders per job scheduling problems

In this paper, we discuss scheduling problems motivated by a real-world production setting found in 300-mm semiconductor wafer fabrication facilities (wafer fabs). Front opening unified pods (FOUPs) transfer wafers in 300-mm wafer fabs. Several orders can be grouped in one FOUP. We study lot and single item processing environments. The total weighted tardiness (TWT) and the weighted number of tardy orders (WNTO) objectives are considered. Mixed integer programming (MIP) formulations are presented for the scheduling problems. We prove that the researched scheduling problems are NP-hard. Grouping genetic algorithms (GGAs) are proposed to form the content of the FOUPs. We compare the performance of the GGAs with another GA from the literature available for the problem with TWT measure based on randomly generated problem instances. It turns out that the GGA outperforms the heuristic from the literature for both environments. For the WTNO measure, we assess the performance of the GGA approach using MIP formulations for small-size problem instances and a GA-based heuristic for large-size problem instances. Again, the GGA performs well with respect to solution quality and amount of computing time.

반도체 웨이퍼 제조공정 클린룸 구조, 공기조화 및 오염제어시스템

Objectives: The purpose of this study was to examine clean room(C/R) structure, air conditioning and contamination control systems and to provide basic information for identifying a correlation between the semiconductor work environment and workers' disease. Methods: This study was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. The C/R structure and air conditioning method were investigated using basic engineering data from documentation for C/R construction. Furthermore, contamination parameters such as airborne particles, temperature, humidity, acids, ammonia, organic compounds, and vibration in the C/R were based on the International Technology Roadmap for Semiconductors(ITRS). The properties of contamination control systems and the current status of monitoring of various contaminants in the C/R were investigated. Results: 200 mm and 300 mm wafer fabrication facilities were divided into fab(C/R) and sub fab(Plenum), and fab, clean sub fab and facility sub fab, respectively. Fresh air(FA) is supplied in the plenum or clean sub fab by the outdoor air handling unit system which purifies outdoor air. FA supply or contaminated indoor air ventilation rates in the 200 mm and 300 mm wafer fabrication facilities are approximately 10-25%. Furthermore, semiconductor clean rooms strictly controlled airborne particles(≤ 1,000 #/ft³), temperature(23±0.5℃), humidity(45±5%), air velocity(0.4 m/s), air change(60-80 cycles/hr), vibration(≤ 1 cm/s²), and differential pressure(atmospheric pressure + 1.0-2.5 mmH2O) through air handling and contamination control systems. In addition, acids, alkali and ozone are managed at less than internal criteria by chemical filters. Conclusions: Semiconductor clean rooms can be a pleasant environment for workers as well as semiconductor devices. However, based on the precautionary principle, it may be necessary to continuously improve semiconductor processes and the work environment.

반도체 작업환경 내 부산물로 생성되는 실리카 입자의 크기, 형상 및 결정 구조

Objectives: This study aimed to elucidate the physicochemical properties of silica powder and airborne particles as by-products generated from fabrication processes to reduce unknown risk factors in the semiconductor manufacturing work environment. Materials and Methods: Sampling was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. Thirty-two powder and airborne by-product samples, diffusion(10), chemical vapor deposition(10), chemical mechanical polishing(5), clean(5), etch process(2), were collected from inner chamber parts from process and 1st scrubber equipment during maintenance and process operation. The chemical composition, size, shape, and crystal structure of silica by-product particles were determined by using scanning electron microscopy and transmission electron microscopy techniques equipped with energy dispersive spectroscopy, and x-ray diffractometry. Results: All powder and airborne particle samples were composed of oxygen(O) and silicon(Si), which means silica particle. The by-product particles were nearly spherical <TEX>$SiO_2$</TEX> and the particle size ranged 25 nm to <TEX>$50{\mu}m$</TEX>, and most of the particles were usually agglomerated within a particle size range from approximately 25 nm to 500 nm. In addition, the crystal structure of the silica powder particles was found to be an amorphous silica. Conclusions: The silica by-product particles generated from the semiconductor manufacturing processes are amorphous <TEX>$SiO_2$</TEX>, which is considered a less toxic form. These results should provide useful information for alternative strategies to improve the work environment and workers' health.

Scheduling jobs with ready times and precedence constraints on parallel batch machines using metaheuristics

In this paper, we discuss a scheduling problem for parallel batch machines where the jobs have ready times. Problems of this type can be found in semiconductor wafer fabrication facilities (wafer fabs). In addition, we consider precedence constraints among the jobs. Such constraints arise, for example, in scheduling subproblems of the shifting bottleneck heuristic when complex job shop scheduling problems are tackled. We use the total weighted tardiness as the performance measure to be optimized. Hence, the problem is NP-hard and we have to rely on heuristic solution approaches. We consider a variable neighborhood search (VNS) scheme and a greedy randomized adaptive search procedure (GRASP) to compute efficient solutions. We assess the performance of the two metaheuristics based on a large set of randomly generated problem instances and based on instances from the literature. The obtained computational results demonstrate that VNS is a very fast heuristic that quickly leads to high-quality solutions, whereas the GRASP is slightly outperformed by the VNS approach. However, the GRASP approach has the advantage that it can be parallelized in a more natural manner compared to VNS.